Overclock your AMD Epyc

Discussion in 'Processors and Motherboards' started by nero243, Feb 5, 2019.

  1. nero243

    nero243 Active Member

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    I... I don't even wan't to respond to this. Let's keep the blood pressure low for today.
     
    #241
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  2. alex_stief

    alex_stief Active Member

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    There is always that one guy...
    He forgot to mention that OC voids warranty :eek:
     
    #242
  3. Wasmachineman_NL

    Wasmachineman_NL Dell Precisions FTW!

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    Never fanboyed for EVGA, the only thing i'm a massive fanboy of are Dell Precisions and Toughbooks.

    tbf though the SR-2 is exactly that: Super Record 2, it's used by those nolifers on HWBOT to set world records on dual Xeons.
     
    #243
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  4. _Robert

    _Robert New Member

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    Thank you for sharing your results. I wonder how clock rates of the 7232p(120W) and 7262(155W) with appropriate cooling would respond to setting TDP 200W in BIOS.
     
    #244
  5. Patriot

    Patriot Moderator

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    Yeah having been in the F@H arena with lots of 2p and 4p setups ... the SR-2 has a very unkind nickname.
    Something about queen of a dog or something. It was a finicky and not well done board.

    Supermicro G34 boards on the other hand, wooooeee 3 8-pin for power was plenty to overclock opterons on. Had Magnycours 4p beating sandybridge 4p.
     
    #245
  6. Sparky'sAdventure

    Sparky'sAdventure New Member

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    Have you personally tested that the DRAM OC works past JEDEC spec? 4200mhz across 8 channels would be pretty insane, and any Micron E-Die based memory should do that relatively easily if vdimm is controllable. Also, if it does go past, do you have any idea if the 7XX2 chips are limited to the same 1900fclk ratio that the desktop and Threadripper chips are capped with?

    Not entirely related but the Zen 2 Threadripper chips don't appear to have an fclk coldbug even on LN2 fullpot according to a few HWBot benchers; I wonder if this carries over to the Epyc chips...
     
    #246
  7. nero243

    nero243 Active Member

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    The only stuff i personally tested in the last few month is, how a FX-8350 holds up in 2019. The answer: not great.

    LN2 benching with Rome wouldn't make much sense, considering on how difficult the unlock seems to be. But it's a little early to even think about it since we haven't made any progress with OCing whatsoever.
     
    #247
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  8. I.nfraR.ed

    I.nfraR.ed New Member

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    Hello,

    Here's the first preliminary version of the "debug" tool. Basically manually setting the addresses and commands.
    SMUDebugTool_v1.0.0.zip

    The software is provided "as is" and using it is on entirely on your own responsibility!
    Trying the test message (0x1) should be safe, but I can't guarantee it.


    upload_2019-12-27_1-15-46.png

    How To
    The app provides several fields
    • CMD Address (hexadecimal) - the base SMU address where the command is sent, or the message address (SMU_ADDR_MSG)
    • RSP Address (hexadecimal) - the response is read from this address
    • ARG Address (hexadecimal) - the address for the first argument. Second argument is calculated automatically
    • Command ID (hexadecimal) - the desired command ID. It's pre-populated with 0x1, which is always a "Test message". If that doesn't return OK, then some of the addresses is incorrect.
    • Argument 0 and Argument 1 (integer) - used for arguments when the command is of type "read". Most of the time you want to set just the Argument 0. Both arguments are used when e.g. you want to set the frequency of a specific CPU core/thread.
    • Status strip at the bottom
    The fields are populated with the default values of the detected CPU Core. Defaults button resets all the fields to the detected values.

    Some examples (for Matisse/Rome/CastlePeak)

    1. Enable Manual Overclock
    Change command to 0x5A and hit Apply. Status should say "OK" and the CPU should be forced to base frequency.
    2. Disable Manual Overclock
    Change command to 0x5B and hit Apply. Status should say "OK" and the CPU should be back to default.
    3. Set Overclock Frequency for all cores
    Manual OC should be enabled first (step 1). Change command to 0x5C and Argument 0 to 4000 (or your frequency of choice). Hit Apply. Status should be OK and a dialog with the response should be the frequency in HEX.​

    I'm still trying to figure out per core overclock, perhaps we don't need the second argument at all. It seem I will need to set the argument to hexadecimal as well.

    It is strange that Matisse has 2 different mailboxes and the command IDs are different, too.

    first set of commands:
    Code:
    SMC_MSG_EnableOverclocking = 0x5A;
    SMC_MSG_DisableOverclocking = 0x5B;
    SMC_MSG_SetOverclockFreqAllCores = 0x5C;
    SMC_MSG_SetOverclockFreqPerCore = 0x5D;
    SMC_MSG_SetOverclockVid = 0x61;
    
    SMC_MSG_SetPPTLimit = 0x53;
    SMC_MSG_SetTDCLimit = 0x54;
    SMC_MSG_SetEDCLimit = 0x55;
    SMC_MSG_SetHTCLimit = 0x56;
    
    SMC_MSG_GetPBOScalar = 0x6C;
    SMC_MSG_SetPBOScalar = 0x6E;
    
    SMC_MSG_GetTctlOffset = 0x70;
    2nd set of commands (with addresses):
    Code:
    const UInt32 SMU_ADDR_MSG = 0x03B10530;
    const UInt32 SMU_ADDR_RSP = 0x03B1057C;
    const UInt32 SMU_ADDR_ARG0 = 0x03B109C4;
    
    const UInt32 SMC_MSG_TestMessage = 0x1;
    const UInt32 SMC_MSG_GetSmuVersion = 0x2;
    const UInt32 SMC_MSG_EnableSmuFeatures = 0x3;
    const UInt32 SMC_MSG_SetTjMax = 0x23;
    const UInt32 SMC_MSG_EnableOverclocking = 0x24;
    const UInt32 SMC_MSG_DisableOverclocking = 0x25;
    const UInt32 SMC_MSG_SetOverclockFreqAllCores = 0x26;
    const UInt32 SMC_MSG_SetOverclockFreqPerCore = 0x27;
    const UInt32 SMC_MSG_SetOverclockVid = 0x28;
    const UInt32 SMC_MSG_SetBoostLimitFrequency = 0x29;
    const UInt32 SMC_MSG_SetBoostLimitFrequencyAllCores = 0x2B;
    const UInt32 SMC_MSG_GetOverclockCap = 0x2C;
    const UInt32 SMC_MSG_MessageCount = 0x2D;
    
    PS: Think I've figured out how to set per core. The Asus tool first sets all core frequency to lowest one, then sends the other command for a single core. The first argument is
    Code:
    0x01200FA0
    for CCX 1, Core 2 (for core # 6), frequency FA0 which in DEC is 4000. So we don't need the second argument.

    Difference between SMU MSG and SMU RSP addresses seems to be 0x4C. So I could probably scan some range of addresses to find the start address. The offset of the ARG is different, though.
     
    #248
    Last edited: Dec 26, 2019
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  9. Wasmachineman_NL

    Wasmachineman_NL Dell Precisions FTW!

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    4200 would be useless on Epyc, because the IF stops scaling about 3800/4000 MHz.
     
    #249
  10. Gordan

    Gordan New Member

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    Is the source code available? I don't use Windows and I would really like to give this a go.
     
    #250
  11. hrvoje.sedlic

    hrvoje.sedlic New Member

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    We have a couple of 7742's on h11dsi-nt and wondering if this would work on this board? Anyone maneged to oc 7742's?

    These don't scale too good in 2cpu setup, so thinking of splitting to two systems with an overclokable mobo. Any advice for a good one?
     
    #251
    Last edited: Dec 31, 2019
  12. ExecutableFix

    ExecutableFix Member

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    Well not yet, but we're definitely making progress. You could try playing with ZenStates and the SMUDebug tool and see if you can get anything to work
     
    #252
  13. hrvoje.sedlic

    hrvoje.sedlic New Member

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    Will do. Any advice for a good overclockable 1cpu mobo?
     
    #253
  14. ExecutableFix

    ExecutableFix Member

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    Pretty much any SP3 board will work, there isn't really a standout one when it comes to VRMs. I personally use a H11SSL-i rev 2 and it's been pretty good for the Naples overclocks. I guess the Asus/Gigabyte boards are just as good
     
    #254
  15. hrvoje.sedlic

    hrvoje.sedlic New Member

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    What is the heighest stable all cores enabled? Compared to base clock out of the box?
     
    #255
  16. ExecutableFix

    ExecutableFix Member

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    On Naples? My ES got 3.4Ghz stable which is pretty decent. I'm not sure what it will be on Rome, but I'm guessing not much more than the max boost clock
     
    #256
  17. hrvoje.sedlic

    hrvoje.sedlic New Member

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    What is standard clock of your sample? Our is 2.4, max boost 3.0, so it should go that higher?
     
    #257
  18. I.nfraR.ed

    I.nfraR.ed New Member

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    Yes. There are also 2 more released versions.
    irusanov/SMUDebugTool

    I'm also a Linux user and would love to port or at least have a tool with similar functionality.
    The windows version is not even close to finish, because there's no documentation. Plus I'm not really a .NET developer. However, I don't have any experience with programming for linux (except Linux/Android kernel). Eventually I can try to make a .NET Core (console) application, similar to the windows app, but that's when (and if) we figure out all the missing bits.

    Edit: These might help you
    FlyGoat/ryzen_nb_smu
    zamaudio/smutool
     
    #258
    Last edited: Dec 31, 2019
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  19. ExecutableFix

    ExecutableFix Member

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    Well the Naples ES has a clockspeed of 1.9Ghz base and 3.0Ghz boost, so it does go higher. But I'm pretty sure that doesn't work the same on Rome. There's not much headroom on the 64C. You might have more luck on the 32C
     
    #259
  20. hrvoje.sedlic

    hrvoje.sedlic New Member

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    Nice. I'm able to get some rome 2 64/128 1.8ghz cpus, these could be a good overclockers then.
     
    #260
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