Bug in Intel Atom C2000 series processors?

Jyrki

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May 14, 2013
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Have you guys looked those reworked boards really carefully? I assume there would be one or two tiny smd resistors added somewhere. I would rather rework solder those myself than wait 2+ weeks for board returning back.

Edit: I looked around docs a bit. I woud guess JTMP1 (TPM header/Port 80 header) has resistor from pin 1 to +3.3V. +3.3V can be found from pin 9 of the same connector, but I would assume it is also available closer of pin 1 somewhere on the board. I don't have photo of back side of PCB and mine is installed in case and running. I would guess resistor is either 100ohm, 8.2kohm or 10kohm.


Edit2,3: Those wondering steppings reported by software. Reported 0 = stepping A0/A1, Reported 8 = stepping B0. I don't know what stepping C0 reports. Also stepping C0 is reported as 8. There is another field showing it is C0 SoC. I assume because cpu part of SoC is unmodified.
 
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weust

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Aug 15, 2014
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I finally had time to send Supermicro an email and received a response this morning.
Was asked to fill out the RMA form and send to the RMA email address.
It got approved already so I will be sending the board tomorrow.

Once it's back I can use it as my FreeBSD poudriere en monitoring server
 
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RageBone

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Jul 11, 2017
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@Jyrki cisco was reported to be switching from the first lpc clock source to the second, which was broken out and not connected to anything else.
Possibly pulled low or what ever, keeping it from degrading.
Hence the pictures of the weird soldered in resistor bridging pads.

There was a discussion on the EEV Forum sifting through some documents and statements deciphering that the board level workaround was a 10K? Resistor between Clock and Data if i remember correctly. I probably don't please look it up again.

Another way of reworking those boards would be to simply swap the CPU with a fixed one, so you won't see any "fixes" like CiSCOs

I have a broken ASRack board from this family and i have looked for the second clock source, but it doesn't look to be even wired in on the board.
It is also extremely hard do follow traces and vias since the BGA layout leaves a ton of space between pads making vias able to be grouped together differently then one sane person would assume.
So XRay would be the only reasonable and not time wasting way of finding that. I sadly don't own one, or have access to such a machine.

On the other hand, many Asrack Atom boards were reported to have other problems, so it might not be the clock gen that keeps my board from posting.
 

AndyYin

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Sep 26, 2019
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@Jyrki cisco was reported to be switching from the first lpc clock source to the second, which was broken out and not connected to anything else.
Possibly pulled low or what ever, keeping it from degrading.
Hence the pictures of the weird soldered in resistor bridging pads.

There was a discussion on the EEV Forum sifting through some documents and statements deciphering that the board level workaround was a 10K? Resistor between Clock and Data if i remember correctly. I probably don't please look it up again.

Another way of reworking those boards would be to simply swap the CPU with a fixed one, so you won't see any "fixes" like CiSCOs

I have a broken ASRack board from this family and i have looked for the second clock source, but it doesn't look to be even wired in on the board.
It is also extremely hard do follow traces and vias since the BGA layout leaves a ton of space between pads making vias able to be grouped together differently then one sane person would assume.
So XRay would be the only reasonable and not time wasting way of finding that. I sadly don't own one, or have access to such a machine.

On the other hand, many Asrack Atom boards were reported to have other problems, so it might not be the clock gen that keeps my board from posting.
I just fixed a bricked Supermicro A1sa7-2750f, the Motherboard is using Intel Atom C2750.

https://www.supermicro.com/manuals/motherboard/Atom_on-chip/MNL-1555.pdf (Page23)
TPM Header/Port 80 Header, A Trusted Platform Module/Port 80 header, located at JTPM1, right beside the DIMMB1 slot.
Pin # Defnition Pin # Defnition
1 LCLK 2 GND
3 LFRAME# 4 <(KEY)>
5 LRESET# 6 NC
7 LAD 3 8 LAD 2
9 +3.3V 10 LAD1
11 LAD0 12 GND
13 NC 14 NC
15 +3V_DUAL 16 SERIRQ
17 GND 18 Ground
19 LPCPD# 20 NC

The fix applied is by putting a 110 ohm pull-up resistor from LPC_CLKOUT0 to +3.3V. (PIN1 and PIN9).
Hope this can help you or others guy may save already bricked MB.

!!!! The red circle is a 110 Ohm resistor, DO NOT Connect the wire directly.
rework.png
 

weust

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Aug 15, 2014
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I got mine back this week, just need to test it. But the form shows it's tested and working so I have no doubt it will be fine.
 

AndyYin

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Sep 26, 2019
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I got mine back this week, just need to test it. But the form shows it's tested and working so I have no doubt it will be fine.
Cool~, RMA is the best way for solve the AVR54 issue, they will replace the SOC to C0 stepping.
 

weust

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Aug 15, 2014
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I did notice no extra soldering of a resistor, so that makes sense.

RMA is indeed the best way, but if RMA wouldn't cover it anymore I would use your trick.
Though I would use some special tape (the brownish one) to really make sure nothing conducts.
 

Vidmo

Member
Feb 3, 2017
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Well, my Supermicro A1SRi-2758F finally had the issue arise today. It was running pfSense and was my primary device. I had another A1SRi-2758F in stand-by mode with all pfSense settings synced up. Just had to move the cable from the cable modem over to the stand-by and fire it up. Off to RMA land now.
 

RageBone

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Jul 11, 2017
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@AndyYin
Wasn't that resistor the Intel proposed board level workaround to keep the clockgen from degrading?

Was yours actually bugged with no LPC clock?

Mine currently fore sure has no Clock.
 

AndyYin

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Sep 26, 2019
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RageBone

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Jul 11, 2017
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Well, i thought the SERIQ pullup was to be a workaround for keeping the LPC from degrading.

Had a deeper look at my Asrack C2550d4i and the interesting part is that it has 25MHz on the LPC clock pin except of the expected 33MHz and the IOclock of the SIO is not there.

Both seem to come from a ICS Clockgen, so the Resistor mod didn't work here.
 

gsrcrxsi

Member
Dec 12, 2018
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Cool~, RMA is the best way for solve the AVR54 issue, they will replace the SOC to C0 stepping.
I assume you can see this in the BIOS? to check if a board you have on hand is or will be affected? the "good" stepping is C0? whats the bad stepping? anything else?
 

LittleDiode

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Apr 26, 2020
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Well, i thought the SERIQ pullup was to be a workaround for keeping the LPC from degrading.

Had a deeper look at my Asrack C2550d4i and the interesting part is that it has 25MHz on the LPC clock pin except of the expected 33MHz and the IOclock of the SIO is not there.

Both seem to come from a ICS Clockgen, so the Resistor mod didn't work here.
Did you have any luck with this @RageBone ? I've got a C2750D4i which either suffers from this, or the dead flash issue, or both. It says in the manual that LPC runs at 33MHz.

Has anyone tried this with the P9A-i line of boards?
 

RageBone

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Jul 11, 2017
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Did you have any luck with this @RageBone ? I've got a C2750D4i which either suffers from this, or the dead flash issue, or both. It says in the manual that LPC runs at 33MHz.

Has anyone tried this with the P9A-i line of boards?
i have spend a considerable amount of time on a C2550d4i and i haven't had success on it.
The LPC clock also seems not to be 33MHz but rather 25MHz.
Nothing i have tried worked.

Doing the 110 Ohm mod caused it to turn on and off after like 2 seconds without posting.

I can't remember if the LPC clock had any signal, i tried to figure out whats on the SuperIO and since there is no datasheet, the nearest info i could get on it made it look like that there is absolutely no clock on the LPC clock line, though that datasheet could be wrong since it is for a different SIO.
 
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