cisco was reported to be switching from the first lpc clock source to the second, which was broken out and not connected to anything else.
Possibly pulled low or what ever, keeping it from degrading.
Hence the pictures of the weird soldered in resistor bridging pads.
There was a discussion on the EEV Forum sifting through some documents and statements deciphering that the board level workaround was a 10K? Resistor between Clock and Data if i remember correctly. I probably don't please look it up again.
Another way of reworking those boards would be to simply swap the CPU with a fixed one, so you won't see any "fixes" like CiSCOs
I have a broken ASRack board from this family and i have looked for the second clock source, but it doesn't look to be even wired in on the board.
It is also extremely hard do follow traces and vias since the BGA layout leaves a ton of space between pads making vias able to be grouped together differently then one sane person would assume.
So XRay would be the only reasonable and not time wasting way of finding that. I sadly don't own one, or have access to such a machine.
On the other hand, many Asrack Atom boards were reported to have other problems, so it might not be the clock gen that keeps my board from posting.