"(there're 2 of them in it, each providing 24 1g ports and 4 10 or 12g ports - it seems one 10g port of each chip is used to provide the 2 SFP+ ports, and probably the 3 remaining high speed interfaces are used to interconnect the two ICs inside the switch)"
well, each chip has 4 10G capable paths. 3 are used for inter-chip communication I'd guess @ 12G (basically more bandwidth then all the ports combined on each chip, so thats good) and one port specified for 1 x 10G port. So, to me that's a full 10Gig path for 1 SFP, and since there's 2 chips, that makes 2 x 10Gig paths, 1 for each SFP.
The way I see it, the only place there "could" be a bottleneck would be via the interconnect. But since each chip only support 24G+10Gig = 34Gig, and the interconnect maxes out at 36Gig, there is no chance of bottleneck. However, the only thing that isn't specified (that I can find) is if the interconnects are running at 12Gbps bidirectional, or asynchronous. I'd think that would be bi-di, so in full path bandwidth that would be 72Gbps, which is still more then enough, assuming all the physical connections are running bi-di as well.