PCI-SIG Starts Work on PCIe 7.0 for 2025 and Why it Matters for Servers

[Cliff Robinson]

The PCI-SIG is working on PCIe 7.0. We explain why PCIe Gen7 will impact the density and utilization of servers in the future

The post PCI-SIG Starts Work on PCIe 7.0 for 2025 and Why it Matters for Servers appeared first on ServeTheHome.

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[discoeels]

So, if I'm not mistaken, DDR5, PCIe 7.0, and 100Gbe lanes would all use PAM4 signaling. Not an EE or anything, but what would be
the implications of that?

 

[i386]

PAM4 means 4 possible signal combinations with one clock:
00 (eg: 1 Volt)
01 (2 Volt)
10 (-1 Volt)
11 (-2 Volt)
That way you can "double" the "bandwidth" using the same frequency.
(Increasing frequency to get more bandwidth is not easy/cheap hence this or other approaches to get more bandwidth/performance)

If you want to triple the bandwidth using the same frequency you would need pam8 (2^3)

 

[ericloewe]

So, if I'm not mistaken, DDR5, PCIe 7.0, and 100Gbe lanes would all use PAM4 signaling. Not an EE or anything, but what would be
the implications of that?

Decreased immunity to noise and significantly more complex transceivers. Since the former is handled by better coding and error correction and the latter will get easier over time as adoption grows, I would not be surprised to see a hybrid PCIe version using the new tech at a slower symbol rate (e.g. PCIe 5.0 bitrates with PCIe 4.0 clocks) for reduced power and complexity in applications where even a single lane is overkill.

 

[discoeels]

Is it easier to have the same signaling for all three?
I chose 400Gbe for my technical writing topic last summer. Hot and power-hungry, too but looks different when factored with the amount of traffic they move. Packets,IO,etc/mW. I don't remember how the ratios were presented.