DDR5 ECC EC4 vs EC8

[ocfguy]

I just read about that there are two kinds of DDR5 ECC DIMMs, x72 (EC4) and x80 (EC8) modules. It seems like most RDIMM modules are EC8, while most UDIMMs are EC4. However, it seems that actual documentation on the differences between EC4 and EC8 can be hard to come by.

Would anyone here be able to explain the differences between the two layouts? Are both SECDED?

 

[Styp]

Afaik:
on-die ECC is 72 bits. (64bits + 8 parity)
'proper' ECC is 80 bits (64 bits + 2x 8 parity)

 

[RolloZ170]

on-die ECC is 72 bits. (64bits + 8 parity)

on-die-ECC do not provide ECC bits to the CPU.
DDR5 UDIMM is 64 bit (with on-die-ECC)

proper' ECC is 80 bits (64 bits + 2x 8 parity)

DDR5 uses two independent channels banks. 2x 32bit + ECC 4/8 bits
there are modules with 2*(32+4) and 2*(32+8)
probably some systems do not make adv. of the two channel bank, work with the 2*32bit in 64+ECC mode like DDR4 is.
or they can work with 4 bits per 32bit databits.
if the modules are ?Rx4 organized, 8bit chips chip can not be used because they have different latency timings.
if the modules are ?Rx8 organized, a 4 bit chip can not be used because they have different latency timings, better use all the same chips.

 

[sam55todd]

This reply doesn't answer the question but provides confirmational evidence on Micron RDIMM modules I have (another thread "Where are the DDR5 ECC UDIMMs?" reply by RolloZ170 mentions their product code starting with MTC10 as EC8 too).

 

[RolloZ170]

I just read about that there are two kinds of DDR5 ECC DIMMs, x72 (EC4) and x80 (EC8) modules

if you check JEDEC.org there is no EC8UDIMM x80 bit.
EC4UDIMM may have 5* 8bit chips per Rank, but the ECC ship is connected with 4 bits ECC only, 4 bits are left unused.

 

[RolloZ170]

Are both SECDED?

depends on the CPU, not the RAM.

 

[RolloZ170]

AMD uses Advanced Memory Device Correction (AMDC).
i don't found any information which algorithm Intel uses actualy.

 

[twin_savage]

Probably kind of an esoteric question: Do you all think that there would be a difference in overclocking potential between EC4 and EC8 RDIMMs?
I just found out today that RDIMMs don't need an XMP profile to overclock on W790.

 

[RolloZ170]

I just found out today that RDIMMs don't need an XMP profile to overclock on W790.

you never need XMP to overclock. it is just more easy.

 

[twin_savage]

you never need XMP to overclock. it is just more easy.

True. I had wrongly assumed that the presence of the RCD on DIMM prevented any overclocking and that somehow the XMP implementation on RDIMM "unlocked" the RCD.

 

[111alan]

True. I had wrongly assumed that the presence of the RCD on DIMM prevented any overclocking and that somehow the XMP implementation on RDIMM "unlocked" the RCD.

What you really need to worry about is that, most ECC memory modules have locked voltage.

 

[111alan]

on-die-ECC do not provide ECC bits to the CPU.
DDR5 UDIMM is 64 bit (with on-die-ECC)

DDR5 uses two independent banks. 2x 32bit + ECC 4/8 bits
there are modules with 2*(32+4) and 2*(32+8)
probably some systems do not make adv. of the two bank, work with the 2*32bit in 64+ECC mode like DDR4 is.
or they can work with 4 bits per 32bit databits.
if the modules are ?Rx4 organized, 8bit chips chip can not be used because they have different latency timings.
if the modules are ?Rx8 organized, a 4 bit chip can not be used because they have different latency timings, better use all the same chips.

Each DDR5 module has two 32bit "channels" to be precise. There are a lot of banks on each module.

EC4= 32bit+4bit per channel
EC8=32bit+8bit per channel

 

[twin_savage]

What you really need to worry about is that, most ECC memory modules have locked voltage.

I thought this would be a function of motherboard BIOS? so far I haven't found any RDIMMs I can't overvolt.... but I haven't tried many yet.

 

[RolloZ170]

I thought this would be a function of motherboard BIOS?

DDR5 have they're own voltage regs on the PCB:
UDIMM 5V -> 1.1V(typical)
RDIMM 12V -> 1.1V(typical)

 

[twin_savage]

DDR5 have they're own voltage regs on the PCB:
UDIMM 5V -> 1.1V(typical)
RDIMM 12V -> 1.1V(typical)

I read Micron's interpretation of the JEDEC spec on PMICs and it doesn't seem like there is a way to voltage lock them, the motherboard can manipulate the PMIC CAMP pin via the SPD hub connection via sideband I3C to set operational values. Perhaps the SPD hub IC could be co-opted to block communication to PMIC to lock voltage?

The reason I'm semi-skeptical on the DIMMs themselves voltage locking is that it is so rare for a motherboard to support voltage adjustments to RDIMMs that it seems kind of redundant to go to the trouble to lock them down.