I'm unconvinced about a single extra lane being that important. How would an arrangement with 1 lane for BMC plus 8 16x controllers be useful in practice? I mean, even if you can hook up the BMC to the extra lane, at minimum you're also supposed to have a standard NIC, which takes one more lane (I'm not sure if you can bypass or mix traffic from the NIC wired to the BMC to the rest of the system to make it work as a standard NIC), and maybe a SATA or two, but these may be unnecessary if you sacrifice 1 NVMe, or if you use an USB Flash Drive, or fully remote fixed storage. Basically, minimum I/O to get a functional system is a NIC, and with a BMC, it will not allow for the 8th controller to work at 16x, maybe 8x with 8 lanes for basic I/O.
Albeit I think that using a small 1 Lane uplink PLX Switch to fanout the extra lane may work...
Also, it seems that there will be a lot of differences between old Naples Motherboards and Rome Motherboards. Rome will not be able to use several new features in old Naples platforms and Naples may not even make a Rome platform functional if it can't support the extra lane for the BMC or whatever other important component is wired there. I suppose that Rome may be expected to be a drop-in replacement for Naples, but that seems to limit it a bit in I/O, and Naples in Rome Motherboards may not even be a good idea at all.
Finally, with these SERDES thing being twice as fast, can they do things like consolidate the 2 lanes per 10G NIC of Zen to a single one, or implement a mixed 6 GBps SATA / 12 GBps SAS? Sounds like a fun idea to have a built in SAS HBA in the Processor itself. Last time I checked that either Intel or AMD tried to include SAS support in the basic platform was the half-working implementation of the
X79 Chipset.
