Inspired by this post I have been investigating if it is possible to edit the NVM of Intel X710 adaptors to allow any brand of SFP module to be used. The good news is, I think it's entirely possible using similar methods to NathanA's post.
First ray of hope is that in this document: https://www.intel.com/content/dam/w...tasheets/xl710-10-40-controller-datasheet.pdf
There are multiple references to the 'qualfied module check' being something that can be enabled or disabled.
Page 136 (note: all my page references are to the PDF page index not the printed page index)
Page 498:
6.3.24.9 PHY capabilities misc0 (0x0008)
This is per-port on the x710 series. Interestingly the documents state the default is 0b (i.e. check is off) so Intel must force the flag to 'on' for their product firmwares. The document notes that these fields are preserved by the update tool - I beleive this is simply so that any changes that manufacturers make to these settings don't get blown away by firmware updates, not a statement that these fields cannot be changes... though we shall see.
The structure of the NVM is slightly more complex than the X520 series. I have not been able to validate yet because I do not have hardware to experiment on right now, but rather than being a fixed monolithic data structure the top level NVM is organised as a list of pointers to other memory locations.
Reverse engineering this from the bit field we need to change backwards..
This is as far as I can go in theory - in the next few days I will have hardware to test with and I will update you!
First ray of hope is that in this document: https://www.intel.com/content/dam/w...tasheets/xl710-10-40-controller-datasheet.pdf
There are multiple references to the 'qualfied module check' being something that can be enabled or disabled.
Page 136 (note: all my page references are to the PDF page index not the printed page index)
4.If link is setup for module connectivity:
• Firmware verifies that the connected module is a qualified module (when enabled).
• Based on module type, optical or direct attach, firmware configures the PCS registers and
the re-timer (when applicable).
• Firmware restarts the link setup.
Further reading reveals that the qualification check is indeed enabled or disabled with a flag in the NVM (EEPROM):If module or PHY qualification is enabled and connected device is not found in the qualified
list, firmware stops the link setup process and reports event to software.
Page 498:
6.3.24.9 PHY capabilities misc0 (0x0008)
Bits | Field Name | Default NVM Value | Description |
15:13 | RESERVED | 000b | Reserved. |
12 | Disable Firmware Link Management | 0b | Used to disable the firmware's link management and enable direct software control of the link parameters for debug. Note:This field is preserved by the Intel NVM update tool. |
11 | Enable Module Qualification | 0b | When, set to 1b, module qualification process is enabled. Note:This field is preserved by the Intel NVM update tool. |
This is per-port on the x710 series. Interestingly the documents state the default is 0b (i.e. check is off) so Intel must force the flag to 'on' for their product firmwares. The document notes that these fields are preserved by the update tool - I beleive this is simply so that any changes that manufacturers make to these settings don't get blown away by firmware updates, not a statement that these fields cannot be changes... though we shall see.
The structure of the NVM is slightly more complex than the X520 series. I have not been able to validate yet because I do not have hardware to experiment on right now, but rather than being a fixed monolithic data structure the top level NVM is organised as a list of pointers to other memory locations.
Reverse engineering this from the bit field we need to change backwards..
- The Enable Module Qualification field is bit 11 of the 'PHY Cababilities misc0' word (Page 496)
- The 'PHY Capabilities misc0' word is located at offset 0x0008 of the 'PHY Capabilites Data Structure 0' (Page 494)
- The 'PHY Capabilities Data Structure 0' is located at 0x07 of the 'EMP Settings' section. The data structures for the other ports (up to four) are at 0x08, 0x09, 0x0A. (Page 291) I am unsure at this point if these are the locations of the actual Structures or further pointers to the structures.
- Finally Table 6-2 (Page 293) confims the pointer to the EMP Settings section is located at word 0x0F of the NVM.
This is as far as I can go in theory - in the next few days I will have hardware to test with and I will update you!