The true reason why SPR is delayed

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111alan

Active Member
Mar 11, 2019
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Haerbing Institution of Technology
8490H stepping E3 QS. non-SNC
8490H_4800.png

SNC4 is even weirder.
8490H_4800_SNC4.png

Inter-die core-to-core latency is about 65/58/77/70(yes, the latency is somehow higher while both cores are in the same die.)

This result is somehow promising, as the inter-die latency on the lower end is actually very close to what we expect on a large complete die. But I doubt something with huge L3 and memory latency issues can actually pass the qualifications.

BTW rendering performances are very bad too. Not allowed to post that for now. I think they are still fixing this thing, as we have already seen E5 stepping units on the list, and the rumored final stepping should be something like G0.