Supermicro EPYC boards

Discussion in 'Processors and Motherboards' started by EffrafaxOfWug, Jun 21, 2017.

  1. realtomatoes

    realtomatoes Active Member

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    try borrowing some hardware from a vendor to test out your company's workload on these systems. we generally, reach out to ours when new gear comes out so we can play, eh test, i meant.
     
    #21
  2. i386

    i386 Well-Known Member

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    #22
  3. loopback14

    loopback14 New Member

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    Yeah, but I can't find them anywhere in Europe yet... any luck in the USA, anybody knows the prices?
     
    #23
  4. i386

    i386 Well-Known Member

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    I asked different shops in germany and they all said it will take a few weeks until supermicro ships them. (One shop said that it will take at least 6 weeks).
    Sadly nobody had a price for these boards :(
     
    #24
  5. loopback14

    loopback14 New Member

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    mindfactory.de? :)
     
    #25
  6. ( )

    ( ) New Member

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    #26
  7. Evan

    Evan Well-Known Member

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    Pretty pricey boards but to be expected I guess
     
    #27
  8. alex_stief

    alex_stief Active Member

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    #28
  9. zir_blazer

    zir_blazer Active Member

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    Supermicro seems to have slighty improved the Block Diagram of their EPYC platforms, since they seem to actually annotate which CPU provides the PCIe Lanes. So far, EPYC seems a bit nightmarish for builds doing heavy Passthrough since you need to make sure that when you create a VM, the entire NUMA Node (CPU, RAM and PCIe Controller) is self contained, and that requires specific knowledge of the Motherboard PCI Topology.

    There seems to be a single Manual for all three H11SSL Motherboards, but the Block Diagram seems to be for the either the H11SSL-C or the H11SSL-NC. This is what I could decode:


    Die 0:
    1 Lane for BMC AST2500 - CPU PCIE_P0 [0] (Also takes 1 USB from CPU1? Why not CPU0? Can't understand the USBs)
    1 Lane for ASM1042 (USB Controller) - CPU PCIE P0 [2]
    1 Lane for LAN1 I210 - CPU PCIE P0 [8]
    1 Lane for LAN2 I210 - CPU PCIE P0 [12]
    16 Lanes for PCIE X16 SLOT 2 - CPU G0 [15:0]
    12 Lanes unaccounted

    Die 1:
    16 Lanes for PCIE X16 SLOT 6 - CPU PCIE P1 [15:0]
    1 Lane for TUSB7340 (USB Controller) - CPU G1 [0]
    4 Lanes for M.2 Slot - CPU G1 [7:3] (Says 3~7, but that should be a typo cause that is 5 Lanes, not 4)
    8 Lanes for PCIE X8 SLOT 1 - CPU G1 [15:8]
    3 Lanes unaccounted

    Die 2:
    16 Lanes for PCIE X16 SLOT 4 - CPU PCIE P2 [0:15]
    8 Lanes for LSI3008 SAS Controller - CPU G2 [15:8]
    According to the Block Diagram, there are 8 SATAs coming from CPU2, which should also take 1 Lane each. As far that I'm aware, Zeppelin could provide 2 SATA per die, so that doesn't seems right unless Zeppelin is more flexible that AMD said when Ryzen was released.
    0-8 Lanes unaccounted

    Die 3:
    8 Lanes for PCIE X8 SLOT 5 - CPU PCIE P3 [0~7]
    8 Lanes for PCIE X8 SLOT 3 - CPU G3 [15:8]
    4 Lanes for NVM1 or 4 SATA - CPU G3 SATA [33:30]
    4 Lanes for NVM2 or 4 SATA - CPU G3 SATA [37:34]
    8 Lanes unaccounted


    EPYC Block Diagrams may require some help...
     
    #29
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