PCIe NVMe HBA FYI
- Thread starter AJXCR
- Start date
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Pricing seems to be consistent from different vendors..Good point, Makes me wanna grab a few before they realize their mistake
What I'd really like to know is what exactly makes the X10DSC+ and X10SRW-F compatible with several of these cards.. Simply a matter of testing, or is there something different on those two boards? The DSC+ has oculink on board, but the SRW-F does not:
I have a X10DRU-i+, 12 more NVMe drives, and two cpu's sitting here in boxes.. if only I had a good way to plug it all together lol.
"...up to 4 samsung 2tb pros..."
I don't know how much better the nvme samsungs are compared to the sata devices. But if they have a similar behaviour under sustained reads/writes than even pci x4 would provide more than enough bandwidth.
Yes if you are needing so much performance then I would say other options may serve a purpose better, 8 x sas3 enterprise ssd for example.
I have no hands on experience with the NVMe Pro's but they don't look as bad as a SATA EVO sure, but don't think they match the enterprise drives for sustained performance.
Can't tell exactly, but the default config for that card is to treat the PCIex16 as 4x4. It likely has to do with both PCIe lane allocation and bifurcation support in the bios.Pricing seems to be consistent from different vendors..
What I'd really like to know is what exactly makes the X10DSC+ and X10SRW-F compatible with several of these cards.. Simply a matter of testing, or is there something different on those two boards? The DSC+ has oculink on board, but the SRW-F does not:
I have a X10DRU-i+, 12 more NVMe drives, and two cpu's sitting here in boxes.. if only I had a good way to plug it all together lol.
> the default config for that card is to treat the PCIex16 as 4x4.
> It likely has to do with both PCIe lane allocation and bifurcation support in the bios
That makes total sense:
with a variety of different jumper settings,
there will need to be logic at the other end
of those circuits to read the jumper settings
and then adjust behavior accordingly.
As such, the BIOS is where that "adjustment"
would need to be made.
(Just thinking out loud here, OK?)
> It likely has to do with both PCIe lane allocation and bifurcation support in the bios
That makes total sense:
with a variety of different jumper settings,
there will need to be logic at the other end
of those circuits to read the jumper settings
and then adjust behavior accordingly.
As such, the BIOS is where that "adjustment"
would need to be made.
(Just thinking out loud here, OK?)