OCP DC-SCM 1.0 Shown at OCP Regional Summit 2023

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oneplane

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Jul 23, 2021
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I hope they also get their board interface on a software level sorted out. The FPGA, however, leads me to believe that the mainboard manufacturer will need to release some bitstreams and firmware tables before this can even work cross-vendor. Even just the non-discoverable buses like LPC would make it nearly impossible to have swappable management boards. At least the management SoC (ASPEED in this case) and base OS (OpenBMC for example) are already universal-ish.

The solution could be as simple as having a USB Mass Storage device embedded on the mainboard that holds a freely readable layout and address/pin location for non-removable items (like slot locations, bus wiring, SPI and LPC addresses) so any DC-SCM board would be able to at least figure out where all the devices to talk to are.

Edit: looking at the spec at https://www.opencompute.org/documents/ocp-dc-scm-spec-rev-1-0-pdf it seems the smart people working on this stuff already thought of this :D The essentially made LPC unsupported and also primarily seem to use eSPI as one of the lowest transport primitives, which is great. They also have two SGPIO's that are used to mux and transport things like #PROCHOT, PMBus, SMBus, chassis information like fans and temps and power control. Pretty neat, let's hope this idea at some time in the future trickles down into non-OCP systems so we can benefit from this in the homelab as well:p

Edit2: but as expected, in the same spec (chapter 6 starting on page 44) they do expect complete firmware replacements needed when trying to use the same DC-SCM in different systems :(
 
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