Motherboard (C621a chipset) support for Xeon W 3000 series

[Spartus]

Do I need a motherboard that explicitly supports Xeon W series
(X12SPA-TF) or does any "Xeon scalable" board work?

Example candidate:

X12SPL-F | Motherboards | Products | Super Micro Computer, Inc.

In general, I really just need pseudo workstation board of any type that can support a Xeon W. There was some stock of X12SPA-TF but it dried up.

Thanks!

 

[RolloZ170]

saw a Xeon W-3335 QS running on a X12SPL-LN4F (X12SPL-F is the same pcb with 2 LAN not soldered)
but 16 PCIe lanes of the Xeon-W are not connected.

 

[Spartus]

That is very interesting, thank you! I'll explore this option (weigh the risk). I unfortunately can't imagine needing a single socket xeon scalable board board if it doesnt work out. Dual socket or whats the point.

 

[Spartus]

I'm happy to report that I just booted a Xeon W-3335 on an X12DAI-N6 (A dual socket board clearly meant for xeon scalable).

 

[Phong Nguyen]

I'm happy to report that I just booted a Xeon W-3335 on an X12DAI-N6 (A dual socket board clearly meant for xeon scalable).

Have you encounter any glitch or incompatibility issue with Xeon W-3335 on X12DAI-N6? I am thinking of running the same CPU under X12SPi-TF. Thanks!

 

[Phong Nguyen]

saw a Xeon W-3335 QS running on a X12SPL-LN4F (X12SPL-F is the same pcb with 2 LAN not soldered)
but 16 PCIe lanes of the Xeon-W are not connected.

Xeon W-3335 supports 64 PCI lanes. Thus we have 48 lanes connected and 16 unconnected. X12SPL-LN4F has 7 PCIe slots. Are you unable to use a particular PCIe slot(s)? Thank you for the info.

 

[Phong Nguyen]

no, just can't use all the lanes of the Xeon W. and Persistant memory is not suported with Xeon W.

X12SPL-LN4F has these PCIe slots.

Lanes Slot
---------------------------------
(16) 2 x PCIe 4.0 x8,
(16) 1 x PCIe 4.0 x16,
(8) 1 x PCIe 4.0 x8 (in x16 slot)
(24) 3 x PCIe 3.0 x8

In total, 64 lanes are required. If 16 lanes on Xeon W-3300 CPU are not connected, then some slots
above are not accessible right?

Maybe I misunderstand the information. If that is the case, please explain. Thanks!

 

[RolloZ170]

In total, 64 lanes are required. If 16 lanes on Xeon W-3300 CPU are not connected, then some slots
above are not accessible right?

ooh we are on X12 not X11.
sorry i was wrong because all 3rd gen SKUs deliver 64 PCIe lanes.
even a Xeon Gold 6326.
forget what i have written.

 

[xf-vc]

Experts needed!

I have an X12SPL-4NF motherboard. Using ES CPU QWAS, I'm encountering a power limit and memory speed lock: 1. I've tried BIOS versions 1.1 to 2.4 and IPMI firmware 1.0.04 to the latest, but neither solved the problem; 2. I later discovered a short circuit to ground on a data line of the VRM MP2978 chip. After replacing all the components, the CPU power limit was unlocked, but memory bandwidth is still <10GHz. However, upgrading the BIOS to version 2.4 has locked everything again.

I checked the CPU ID using AIDA64, and the power limit is unlocked.

I contacted Supermicro customer service, and they said they don't support ES CPUs.

I'm desperate and urgently need your help.

 

[RolloZ170]

I checked the CPU ID using AIDA64, and the power limit is unlocked.

i guess you made a misinterpretation:
in that context unlocked means you can adjust it up to the given max. value.

[General Information]
Processor Name:    Intel Xeon Gold -2900
Original Processor Frequency:    2900.0 MHz
Original Processor Frequency [MHz]:    2900
       
CPU ID:    000606A6
CPU Brand Name:    Genuine Intel(R) CPU 0000%@
CPU Vendor:    GenuineIntel
CPU Stepping:    D0
CPU Code Name:    Ice Lake-SP
CPU Technology:    10 nm
CPU QDF:    QWAS (ES2)
CPU Thermal Design Power (TDP):    205.0 W
CPU Power Limits (Max):    Power = 780.00 W, Time = 32.00 sec
CPU Power Limit 1 (Long Duration)/Processor Base Power (PBP):    Power = 205.00 W, Time = 1.00 sec [Unlocked]
CPU Power Limit 2 (Short Duration)/Maximum Turbo Power (MTP):    Power = 246.00 W, Time = 1.00 sec [Unlocked]
Configurable TDP Level 1 (Down):    205.00 W (50.50 W - 780.00 W), 2600 MHz
Configurable TDP Level 2 (Up):    205.00 W (50.50 W - 780.00 W), 2300 MHz
Current Configurable TDP Level:    Nominal (Legacy) [Locked]
CPU Max. Junction Temperature (Tj,max):    107 °C
CPU Type:    Engineering Sample
CPU Platform:    Socket P+ (LGA4189)
Microcode Update Revision:    D0001E0
Favored Cores List:    9, 11, 7, 8, 15, 3, 4, 5, 6, 13, 1, 2, 12, 10, 14, 16
       
Number of CPU Cores:    16
Number of Logical CPUs:    32
       
[Operating Points]
CPU MFM (Low Power):    800.0 MHz = 8 x 100.0 MHz
CPU LFM (Minimum):    800.0 MHz = 8 x 100.0 MHz
CPU HFM (Base):    2900.0 MHz = 29 x 100.0 MHz
CPU Turbo Max:    3600.0 MHz = 36 x 100.0 MHz [Unlocked]
Turbo Ratio Limits - IA/SSE, Fused:    36x (1-8c), 35x (9-16c)
Turbo Ratio Limits - IA/SSE, Resolved:    36x (1-8c), 35x (9-16c)
Turbo Ratio Limits - AVX2, Fused:    35x (1-8c), 34x (9-16c)
Turbo Ratio Limits - AVX2, Resolved:    35x (1-8c), 34x (9-16c)
Turbo Ratio Limits - AVX-512, Fused:    35x (1-8c), 34x (9-10c), 33x (11-12c), 31x (13-14c), 30x (15-16c)
Turbo Ratio Limits - AVX-512, Resolved:    35x (1-8c), 34x (9-10c), 33x (11-12c), 31x (13-14c), 30x (15-16c)
CPU Current:    1800.0 MHz = 18 x 100.0 MHz @ 0.8324 V
LLC/Ring Maximum:    2400.0 MHz = 24.00 x 100.0 MHz
LLC/Ring Current:    2400.0 MHz = 24.00 x 100.0 MHz @ 1.0699 V
       
CPU Bus Type:    Intel Ultra Path Interconnect (UPI) v1.0
Number of UPI Links per CPU:    3
       
[IA Overclocking]
Voltage Offset:    Supported
Voltage Override:    Supported
Ratio Overclocking:    Not Supported
Fused Ratio Limit:    36x
OC Ratio Limit:    N/A
Voltage Mode:    Interpolative
Voltage Offset:    0 mV
[CLR (CBo/LLC/Ring) Overclocking]
Voltage Offset:    Supported
Voltage Override:    Supported
Ratio Overclocking:    Not Supported
Fused Ratio Limit:    24x
OC Ratio Limit:    N/A
Voltage Mode:    Interpolative
Voltage Offset:    0 mV
[GT (Unslice) Overclocking]
Voltage Offset:    Supported
Voltage Override:    Not Supported
Ratio Overclocking:    Not Supported
Fused Ratio Limit:    N/A
OC Ratio Limit:    N/A
Voltage Mode:    Interpolative
Voltage Offset:    0 mV
       
[Cache and TLB]
L1 Cache:    Instruction: 16 x 32 KBytes, Data: 16 x 48 KBytes
L2 Cache:    Integrated: 16 x 1280 KBytes
L3 Cache:    36 MBytes
Instruction TLB:    4KB/2MB/4MB Pages, 8-way set associative, 1 set
Unified TLB:    4KB/2MB/4MB Pages, 8-way set associative, 128 sets