On Ethernet everybody expects that ten lines of 1Gbit ports will easily fit and flow through a 10Gbit uplink and packets just naturally get accelerated (or slowed) down as they pass one way (or the other).
So with PCIe now out in the wild with versions 1-5 and a single PCIe 5.0 lane delivering the equivalent of 16 PCIe 1.0 lanes I wonder if PCIe 'switch chips' switch packets or lanes?
I guess the main difference would be buffering vs. cut-through processing.
PCIe data really does seem to be passed in packets, which also seem to be limited in size, which should make buffering possible. Yet my impression is that lanes are negotiated end-to-end and not hop-to-hop, even if speeds seem negotiated hop-to-hop. There doesn't seem to be any facility to switch between lane counts and data rates, aggregation and disaggregation even if facilities for oversubscription clearly exist.
The background is mostly my frustration with how the few precious PCIe v4/5 lanes on modern SoCs get wasted by older PCIe v2/3 hardware, when a 'true' switch should make that far more efficient.
E.g. an Aquantia AQC107 10Gbase-T Ethernet NIC (4 lanes of PCIe 2) only requires the bandwidth of a single lane of PCIe 4.0 (as evidenced by the AQC113, which unfortunately nobody seems to sell as an add-on card), but without a switch chip would grab 4 lanes of PCIe 5.0 on a modern mainboard for a quarter of its potential.
Or similarly a quad M.2 to PCIe adapter, which currently tends to just grab 16 bifurcated lanes and pass them on trace-by-trace, when a switch based approach would be far more useful. E.g. a PCIe 5 capable x4 link to the slot, whilst you reuse a set of older PCIe 3.0 based NVMe drives for aggregate capacity and performance (I'm aware of Highpoint-Tech's NVMe RAID adapters, but those also just seem to do lane switching).
In a way having X670 chips, downstream devices and expansion 'opportunities' as add-in boards on a Ryzen 7000 backplane seems more sensible that the current static allocations.
I've been trying to find out what's going on searching the web and reading specs, but articles never go to that level of detail, while specs drown into detail before they outline concepts.
So please can someone enlighten me?
So with PCIe now out in the wild with versions 1-5 and a single PCIe 5.0 lane delivering the equivalent of 16 PCIe 1.0 lanes I wonder if PCIe 'switch chips' switch packets or lanes?
I guess the main difference would be buffering vs. cut-through processing.
PCIe data really does seem to be passed in packets, which also seem to be limited in size, which should make buffering possible. Yet my impression is that lanes are negotiated end-to-end and not hop-to-hop, even if speeds seem negotiated hop-to-hop. There doesn't seem to be any facility to switch between lane counts and data rates, aggregation and disaggregation even if facilities for oversubscription clearly exist.
The background is mostly my frustration with how the few precious PCIe v4/5 lanes on modern SoCs get wasted by older PCIe v2/3 hardware, when a 'true' switch should make that far more efficient.
E.g. an Aquantia AQC107 10Gbase-T Ethernet NIC (4 lanes of PCIe 2) only requires the bandwidth of a single lane of PCIe 4.0 (as evidenced by the AQC113, which unfortunately nobody seems to sell as an add-on card), but without a switch chip would grab 4 lanes of PCIe 5.0 on a modern mainboard for a quarter of its potential.
Or similarly a quad M.2 to PCIe adapter, which currently tends to just grab 16 bifurcated lanes and pass them on trace-by-trace, when a switch based approach would be far more useful. E.g. a PCIe 5 capable x4 link to the slot, whilst you reuse a set of older PCIe 3.0 based NVMe drives for aggregate capacity and performance (I'm aware of Highpoint-Tech's NVMe RAID adapters, but those also just seem to do lane switching).
In a way having X670 chips, downstream devices and expansion 'opportunities' as add-in boards on a Ryzen 7000 backplane seems more sensible that the current static allocations.
I've been trying to find out what's going on searching the web and reading specs, but articles never go to that level of detail, while specs drown into detail before they outline concepts.
So please can someone enlighten me?