Heres a collection of ES or Research MCM CPUs that Intel was teasing a month ago (July), and since I didnt see them get posted here (or much of anywhere really. A reddit thread, tom's hardware, twitter and some foreign language websites, based on google reverse image search.) I figured I'd put them up and provide a bit of context around what was shown, and we can see the stark differences in design philosophy that AMD and Intel currently have:
Pictured: Bottom left - Dual CPU die chip w/ 8x HBM stacks, package uses Knights Landing Xeon Phi keying (See ref 1). Top and Right: Unknown 10nm CPU diess surrounded by other chips, some of which are HBM stacks, but others are unknown, possibly FPGAs, accelerators, IO adapters, etc. Note that none of the chips use Icelake/Cooperlake SP keying (See ref 2), and all the CPU dies are enormous affairs, near the reticle limit, putting them at nearly 2x as large as AMD's IO die (See ref 3).
Source: David Schor on Twitter
Pictured: The "Xeon Phi" keyed chip with 2x CPU Dies and 8x HBM stacks. Note the keying is exactly the same as the Knights landing, even relative to pin A1 denoted by the triangle (See ref 1)
Pictured: Unkeyed chip with a single large CPU die, 2 stacks of HBM, 4 small unknown dies, and a large unknown die, which is probably an accelerator of some sort (NN or GPU?) or an FPGA.
Pictured: Bare package, also unkeyed, with co-EMIB running between where the (presumably) two CPU dies would sit
Pictured: A wafer of presumably EMIB/co-EMIB dies? Not sure, couldnt find any context behind that picture.
Source: Anshel Sag on Twitter
References:
Ref 1:
Pictured: A knights landing xeon phi with omnipath. Couldnt find a good delided picture of a non-omnipath KNL chip. Note the keying on the right side (normally the left would be a mirror of the right when there is no omnipath), and also its position relative to the A1 triangle. This matches up with the "Xeon phi" dual CPU die looking chip with the 8x HBM stacks.
Source: nl.hardware.info via google images
Ref 2:
Pictured: An icelake ES, notice how the keying is along the long side rather than the short side of the CPU
Source: https://www.servethehome.com/first-pictures-of-intel-ice-lake-xeon-server-chips/
Ref 3:
Pictured: Left - Epyc Gen1 (Zen1, 4x CPU SOC Dies), Right - Epyc Gen2 (Zen2, 8x CPU Dies, 1x IO die). The Epyc SP3 package is within 2 millimeters on both axis the same size as the Icelake/Cooperlake and Cascakelake/Skylake packages. It is slightly wider but slightly shorter. Note that even though the IO die looks big compared to the CPU chiplets, the CPU chiplets are roughly the same size as the HBM stacks intel was using, and the IO die is actually not all that big by comparison to the total package. The capacitors around the edge of the package take up a good deal of area under the IHS. Rumor has it that AMD will also be pursuing adding HBM to some Epyc Milan SKUs too.
Source: https://www.nextplatform.com/2019/08/07/amd-doubles-down-and-up-with-rome-epyc-server-chips/
Pictured: Bottom left - Dual CPU die chip w/ 8x HBM stacks, package uses Knights Landing Xeon Phi keying (See ref 1). Top and Right: Unknown 10nm CPU diess surrounded by other chips, some of which are HBM stacks, but others are unknown, possibly FPGAs, accelerators, IO adapters, etc. Note that none of the chips use Icelake/Cooperlake SP keying (See ref 2), and all the CPU dies are enormous affairs, near the reticle limit, putting them at nearly 2x as large as AMD's IO die (See ref 3).
Source: David Schor on Twitter
Pictured: The "Xeon Phi" keyed chip with 2x CPU Dies and 8x HBM stacks. Note the keying is exactly the same as the Knights landing, even relative to pin A1 denoted by the triangle (See ref 1)
Pictured: Unkeyed chip with a single large CPU die, 2 stacks of HBM, 4 small unknown dies, and a large unknown die, which is probably an accelerator of some sort (NN or GPU?) or an FPGA.
Pictured: Bare package, also unkeyed, with co-EMIB running between where the (presumably) two CPU dies would sit
Pictured: A wafer of presumably EMIB/co-EMIB dies? Not sure, couldnt find any context behind that picture.
Source: Anshel Sag on Twitter
References:
Ref 1:
Pictured: A knights landing xeon phi with omnipath. Couldnt find a good delided picture of a non-omnipath KNL chip. Note the keying on the right side (normally the left would be a mirror of the right when there is no omnipath), and also its position relative to the A1 triangle. This matches up with the "Xeon phi" dual CPU die looking chip with the 8x HBM stacks.
Source: nl.hardware.info via google images
Ref 2:
Pictured: An icelake ES, notice how the keying is along the long side rather than the short side of the CPU
Source: https://www.servethehome.com/first-pictures-of-intel-ice-lake-xeon-server-chips/
Ref 3:
Pictured: Left - Epyc Gen1 (Zen1, 4x CPU SOC Dies), Right - Epyc Gen2 (Zen2, 8x CPU Dies, 1x IO die). The Epyc SP3 package is within 2 millimeters on both axis the same size as the Icelake/Cooperlake and Cascakelake/Skylake packages. It is slightly wider but slightly shorter. Note that even though the IO die looks big compared to the CPU chiplets, the CPU chiplets are roughly the same size as the HBM stacks intel was using, and the IO die is actually not all that big by comparison to the total package. The capacitors around the edge of the package take up a good deal of area under the IHS. Rumor has it that AMD will also be pursuing adding HBM to some Epyc Milan SKUs too.
Source: https://www.nextplatform.com/2019/08/07/amd-doubles-down-and-up-with-rome-epyc-server-chips/