Back in the old 5500 series processors, Intel was a lot more specific when it comes to running two different CPUs. In the end, don't try it since Intel only validate very similar CPUs on dual CPU configuration.
Here's the exact quote:
While Intel does nothing to prevent processors from operating together, some
combinations] may not be supported due to limited validation, which may result in
uncharacterized errata. Coupling this fact with the large number of Intel Xeon
processor 5500 series attributes, the following population rules and stepping matrix
have been developed to clearly define supported configurations.
1. Processors must be of the same power—optimization segment. This insures
processors include the same maximum Intel QuickPath Interconnect and DDR3
operating speeds and cache sizes.
2. Processors must operate at the same core frequency. Note, processors within the
same power-optimization segment supporting different maximum core frequencies
(for example, a 2.93 GHZ / 95 W and 2.66 GHZ/ 95 W) can be operated within a
system. However, both must operate at the highest frequency rating commonly
supported. Mixing components operating at different internal clock frequencies is
not supported and will not be validated by Intel.
3. Processors must share symmetry across physical packages with respect to the
number of logical processors per package, number of cores per package {but not
necessarily the same subset of cores within the packages), number of Intel
QuickPath Interconnect interfaces, and cache topology.
4. Mixing dissimilar steppings is only supported with processors that have identical
Extended Family, Extended Model, Processor Type, Family Code and Model Number
as indicated by the function 1 of the CPUID instruction. Mixing processors of
different steppings but the same model (as per CPUID instruction) is supported.
Details regarding the CPUID instruction are provided in the AP—485,
Intei® Processor Identi?cation and the CPUID Instruction application note and the
Intei® 64 and I/4-32 Architectures Software Developers Manual, Volume 2A.
5. After AND’ing the feature flag and extended feature flags from the installed
processors, any processor whose set of feature flags exactly matches the AND'ed
feature flags can be selected by the BIOS as the BSP. If no processor exactly
matches the AND’ed feature flag values, then the processor with the numerically
lower CPUID should be selected as the BSP.
6. Intel requires that the proper microcode update be loaded on each processor
operating within the system. Any processor that does not have the proper
microcode update loaded is considered by Intel to be operating out of specification
7. Customers are fully responsible for the validation of their system configuration.
When it comes to E5-2600, Intel speaks in more general terms:
Intel supports and validates two and four-processor configurations only in which all
processors operate with the same Intel® Quick-(Path Interconnect frequency, core
frequency, power segment, and have the same internal cache sizes. Mixing
components operating at different internal clock frequencies is not supported and
will not be validated by Intel. Combining processors from different power segments
is also not supported.
Processors within a system must operate at the same frequency per bits [15:81 of the
FLEX_RATIO MSR (Address: 194h); however, this does not apply to frequency
transitions initiated due to thermal events, Extended HALT, Enhanced Intel SpeedStep
Technology transitions signal. Please refer to the Intei® Xeon Processor E5 v2
Product Family Processor Datasheet, Volume Two: Registers for details on the
FLEX_RATIO MSR and setting the processor core frequency.
Not all operating systems can support dual processors with mixed frequencies. Mixing
processors of different steppings but the same model (as per CPUID instruction) is
supported provided there is no more than one stepping delta between the processors,
for example, S and 5+1.
S and S+1 is defined as mixing of two CPU steppings in the same platform where one
CPU is S (stepping) = CPUID.(EAX=01h):EAX[3:0], and the other is S+1 =
CPUID.(EAX=01h):EAX[3:0]+1. The stepping ID is found in EAX[3:0] after executing
the CPUID instruction with Function 01h.
Details regarding the CPUID instruction are provided in the AP-485, Intel® Processor
Identification and the CPUID Instruction application note, also refer to the Intel®
Xeon® Processor E5 V2 Product Family Speci?cation Update.
