I agree that ECC is a must. If I'm not mistaken, DDR5 will not have the option to not use ECC, just the level of detection and recovery.
No, the relationship between ECC and DDR5 has caused a lot of confusion.
Because the reliability of the DRAM cells has decreased in modern memories, all DDR5 chips will use ECC internally, to restore the memory reliability to be at the traditional levels, exactly like the flash memories used in SSDs use error-correcting codes internally, otherwise their reliability would be unacceptable.
In any reliable computer, it is required to use an end-to-end ECC, between the CPU and the memory cells, in order to detect (and correct when possible) all the errors, not only those caused by faults in the memory cells, but also the errors caused by electrical noise, oxidized contacts in the DIMM sockets, and so on.
The DDR5 unbuffered DIMMs are available in ECC and in non-ECC variants, exactly like the DDR4 UDIMMs.
The ECC DDR5 UDIMMs have a width of 80, instead of the 72 width of ECC DDR4 UDIMMs, because 1 DDR5 UDIMM has two 32-bit memory channels, instead of one 64-bit memory channel, like DDR4. In DDR5, each 32-bit channel is extended by 8 bits, becoming a 40-bit memory channel with ECC.
Unfortunately, for now, the ECC DDR5 UDIMMs cost almost double the price of the ECC DDR4 UDIMMs, but hopefully their price will decrease towards the end of the year.
Most of the new motherboards with the W680 chipset for the Alder Lake i3/i5/i7/i9 CPUs need ECC DDR5 UDIMMs, but there is at least one such MB (from Gigabyte) which still uses the old ECC DDR4 UDIMMs, to take advantage of their much lower price.
The AM5 boards for Zen 4 that will support ECC will also need ECC DDR5 UDIMMs, to enable the ECC function.