AMD EPYC Naples Memory Population Performance Impact

[Patrick Kennedy]

We test the performance impact of AMD EPYC Naples memory to see how much performance can be gained by moving from one or two DIMMs installed to filling all eight memory channels.

The post AMD EPYC Naples Memory Population Performance Impact appeared first on ServeTheHome.

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[BackupProphet]

This is awesome stuff Patrick!

 

[BlackArchon]

I really have hoped for a few more benchmarks. Also a configuration like two channels populated on die 1 and 3, and no RAM on dies 2 and 4 would be interesting.

 

[Patrick]

I really have hoped for a few more benchmarks. Also a configuration like two channels populated on die 1 and 3, and no RAM on dies 2 and 4 would be interesting.

Data got repetitive after awhile and this takes quite a long time to generate since it requires physical access to the box to swap DIMMs.


On the die 1 and 3 I am not sure why it is hard to extrapolate. Single to dual channel is essentially 4 to 8. Two die populated to four is 2 to 4.

Perhaps when we publish the 32C results we will do more, but two dies with memory access is dumb.

Also, there is an architectural reason you would never do this. If you are constantly accessing RAM over IF your PCIe bandwidth chokes die to die. You have more or less PCIe 3.0 x16 between each die with current IF. If you are doing PCIe transfer and RAM transfer on the same IF link, one has to suffer because there is not enough bandwidth.

 

[BlackArchon]

I'm asking specifically for this configuration because it is rumored that this would be the memory configuration for Threadripper 2. If this is true (and not one channel per die), I'm interested in the performance impact.

 

[Patrick]

I know why people are asking.

 

[TXAG26]

@Patrick - any plans to release a similar article that discusses AMD Epyc ROME memory population performance impacts? I think a lot of us would like to know the impact of only populating 4 channels vs 8 channels with the new memory controller on ROME CPUs.

 

[TXAG26]

Any plans to release a similar article that discusses AMD Epyc ROME memory population performance impacts? I think a lot of us would like to know the impact of only populating 4 channels vs 8 channels with the new memory controller on ROME CPUs.

 

[ari2asem]

reviving this old thread, with a question...

i red the article. when i use 4 dimms per cpu, is the best inbetween way of money/performance.

but what happens when i use 5 dimms per cpu? is the memory running in single channel mode with 5 dimms?

because when i had 3 dimms with my threadripper 1920x (amd x399 chipset), my memory was in single channel mode.
when i removed 1 dimm (so i had 2 dimms on the mainboard), my memory was running in dual channel mode.

is there something similar with epyc naples?

2nd question...what if i install 6 dimms per cpu? in which mode runs the memory? still single channel? or triple channel?

because i have now 2* epyc 7551 with 10 dimms (5 dimms per 1 cpu). and i would like to know how many dimms per cpu is better for me.
4 dimms, 5 dimms or 6 dimms ?
please, don't suggest 8 dimms because i know that it is the best option.

i just want to know the answer for option 4, 5 or 6 dimms.

thanks in advance,
erik

 

[ari2asem]

another question.....can we mix different types of dimms ? ecc-reg (RDimm) and Load Reduced Dimm (LRDimm) on the same board?

i have experience mixing different brands with the same specs, but never mixed different specs dimms together.

any idea??

 

[TXAG26]

No, I’ve never heard of being able to mix different types. Mixing different speeds is fine as everything just runs at the slowest common speed.

 

[ari2asem]

another revive and kind request....any plans to do same test with epyc rome ??

or do we expect more or less the same result for rome, as for naples ??