AMD EPYC Naples Memory Population Performance Impact

Discussion in 'STH Main Site Posts' started by Patrick Kennedy, Jul 31, 2018.

  1. #1
    eva2000 likes this.
  2. BackupProphet

    BackupProphet Well-Known Member

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    This is awesome stuff Patrick!
     
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  3. BlackArchon

    BlackArchon Member

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    I really have hoped for a few more benchmarks. Also a configuration like two channels populated on die 1 and 3, and no RAM on dies 2 and 4 would be interesting. :)
     
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  4. Patrick

    Patrick Administrator
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    Data got repetitive after awhile and this takes quite a long time to generate since it requires physical access to the box to swap DIMMs.


    On the die 1 and 3 I am not sure why it is hard to extrapolate. Single to dual channel is essentially 4 to 8. Two die populated to four is 2 to 4.

    Perhaps when we publish the 32C results we will do more, but two dies with memory access is dumb.

    Also, there is an architectural reason you would never do this. If you are constantly accessing RAM over IF your PCIe bandwidth chokes die to die. You have more or less PCIe 3.0 x16 between each die with current IF. If you are doing PCIe transfer and RAM transfer on the same IF link, one has to suffer because there is not enough bandwidth.
     
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  5. BlackArchon

    BlackArchon Member

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    I'm asking specifically for this configuration because it is rumored that this would be the memory configuration for Threadripper 2. If this is true (and not one channel per die), I'm interested in the performance impact. :)
     
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  6. Patrick

    Patrick Administrator
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    I know why people are asking. ;)
     
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  7. TXAG26

    TXAG26 Member

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    @Patrick - any plans to release a similar article that discusses AMD Epyc ROME memory population performance impacts? I think a lot of us would like to know the impact of only populating 4 channels vs 8 channels with the new memory controller on ROME CPUs.
     
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  8. TXAG26

    TXAG26 Member

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    Any plans to release a similar article that discusses AMD Epyc ROME memory population performance impacts? I think a lot of us would like to know the impact of only populating 4 channels vs 8 channels with the new memory controller on ROME CPUs.
     
    #8
    gigatexal likes this.
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