Environment size: 2356/8188 bytes
Octeon evb7000(ram)# resetSPI stage 1 bootloader
SPI ID: c2:20:17:c2:20
header found at offset 0x1f40
Image 1.2: address: 0xffffffff81000000, header length: 192, data length: 8608
Validating data...
Starting next bootloader at 0xffffffff81000000
SPI stage 1.5 bootloader
SPI ID: c2:20:17:c2:20
Header 1 found at offset 0x10000
Header 2 found at offset 0x80000
Header 3 found at offset 0x100000
Found bootloaders, booting bootloader 2 of 3 at offset 0x80000.
Starting next bootloader at 0xffffffff81000000
Board type: EVB7000
U-Boot 2013.07 ACCTON Version 0.1.0.12 (Build time: Sep 15 2017 - 14:26:10)
Octeon unique ID: 0a8000104019f31e04c1
Found DDR configuration for EVB7000
Cavium Inc. OCTEON SDK version 3.1.2-p11, build 600: $Revision: 162698 $
EARLY FILL COUNT : 22, cpu_hertz:1600000000, ddr_hertz:667000000
LMC0 Asserting DDR_RESET_L
DDR Reference Hertz = 50000000
clkr: 0, en[5]: 6, clkf: 79, pll_MHz: 4000, ddr_hertz: 666666666, error: 333334
clkr: 0, en[2]: 3, clkf: 39, pll_MHz: 2000, ddr_hertz: 666666666, error: 333334
clkr: 1, en[2]: 3, clkf: 79, pll_MHz: 2000, ddr_hertz: 666666666, error: 333334
clkr: 2, en[2]: 3, clkf: 119, pll_MHz: 2000, ddr_hertz: 666666666, error: 333334
clkr: 2, en[1]: 2, clkf: 79, pll_MHz: 1333, ddr_hertz: 666666666, error: 333334
clkr: 0, en[5]: 6, clkf: 79, pll_MHz: 4000, ddr_hertz: 666666666, error: 333334 <==
LMC0 De-asserting DDR_RESET_L
LMC0: Measured DDR clock: 666666654, cpu clock: 1600000000, ddr clocks: 111111339
LMC0: measured speed: 666666654 hz
Initializing node 0 DDR interface 0, DDR Clock 666666654, DDR Reference Clock 50000000, CPUID 0x000d9602
DDR SPD Table:
LMC0 DIMM 0: DDR3 Undefined, ECC chksum: 45462 1.5V
row bits: 16, col bits: 10, bank bits: 3, banks: 8, ranks: 2, dram width: 8, size: 4096 MB
Medium Timebase (MTB) : 125 ps
Minimum Cycle Time (tCKmin) : 1500 ps
Minimum CAS Latency Time (tAAmin) : 13125 ps
Write Recovery Time (tWR) : 15000 ps
Minimum RAS to CAS delay (tRCD) : 13125 ps
Minimum Row Active to Row Active delay (tRRD) : 6000 ps
Minimum Row Precharge Delay (tRP) : 13125 ps
Minimum Active to Precharge (tRAS) : 36000 ps
Minimum Active to Active/Refresh Delay (tRC) : 49125 ps
Minimum Refresh Recovery Delay (tRFC) : 260000 ps
Internal write to read command delay (tWTR) : 7500 ps
Min Internal Rd to Precharge Cmd Delay (tRTP) : 7500 ps
Minimum Four Activate Window Delay (tFAW) : 30000 ps
DDR Clock Rate (tCLK) : 1500 ps
Core Clock Rate (eCLK) : 625 ps
DRAM Interface width: 32 bits +ECC
------ Board Custom Configuration Settings ------
MIN_RTT_NOM_IDX : 1
MAX_RTT_NOM_IDX : 5
MIN_RODT_CTL : 1
MAX_RODT_CTL : 5
MIN_CAS_LATENCY : 0
OFFSET_EN : 1
OFFSET_UDIMM : 2
OFFSET_RDIMM : 2
DDR_RTT_NOM_AUTO : 1
DDR_RODT_CTL_AUTO : 1
RLEVEL_COMP_OFFSET : 0
RLEVEL_COMPUTE : 0
DDR2T_UDIMM : 1
DDR2T_RDIMM : 1
FPRCH2 : 2
PTUNE_OFFSET : 1
NTUNE_OFFSET : -2
-------------------------------------------------
Desired CAS Latency : 9
CAS Latencies supported in DIMM : 5 6 7 8 9
CAS Latency : 9
LMC_SCRAMBLE_CFG0 : 0x0000000000000000
LMC_SCRAMBLE_CFG1 : 0x0000000000000000
LMC_CONFIG : 0x50191d0a2c290086
LMC_CONTROL : 0x000007801f038024
TIMING_PARAMS0 : 0x000064112ccc3400
TIMING_PARAMS1 : 0x0000f2bd34592570
CAS Write Latency CWL, [CSR] : 7, [0x2]
Write recovery for auto precharge WRP, [CSR] : 10, [0x5]
MODEREG_PARAMS0 : 0x0000000000a29002
RTT_NOM 0, 0, 0, 40 ohms : 0,0,0,3
RTT_WR 0, 0, 0, 0 ohms : 0,0,0,0
DIC 40, 40, 40, 40 ohms : 0,0,0,0
MODEREG_PARAMS1 : 0x0000000000000600
MODEREG_PARAMS2 : 0x0000000000000000
LMC_NXM : 0x000000000000550c
WODT_MASK : 0x0000000000000101
RODT_MASK : 0x0000000000000000
DYN_RTT_NOM_MASK : 0x00
DQX_CTL : 4, 34 ohms
CK_CTL : 4, 34 ohms
CMD_CTL : 4, 34 ohms
CONTROL_CTL : 4, 34 ohms
COMP_CTL2 : 0x0001271a00034444
PHY_CTL : 0x0000001200000000
PHY_CTL : 0x0000001200200000
Read ODT_CTL : 0x3 (40 ohms)
EXT_CONFIG : 0x00000000000c0001
Performing Write-Leveling
MODE32B : 1
Rank(0) Wlevel Debug Results : 00000 00000 00000 00000 000f0 000f0 00078 0001e 0000f
Rank(0) Wlevel Rank 0x3, 0x0000600000420800 : 0 0 0 0 4 4 2 0 0
Rank(1) Wlevel Debug Results : 00000 00000 00000 00000 000f0 00070 0003c 0001e 0000f
Rank(1) Wlevel Rank 0x3, 0x0000600000420800 : 0 0 0 0 4 4 2 0 0
MODE32B : 1
Waiting 159448 usecs for ZQCS calibrations to start
Performing Read-Leveling
RLEVEL_CTL : 0x00000000553c3f20
RLEVEL_OFFSET : 2
RLEVEL_OFFSET_EN : 1
RTT_NOM 0, 0, 0, 40 ohms : 0,0,0,3
Read ODT_CTL : 0x5 (120 ohms)
Rank(0) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 003f0 001f8 001ff 000ff 000fe
Rank(0) Rlevel Rank 0x3, 0x00C5145147186145 : 5 5 5 5 7 6 6 5 5 (30)
Rank(1) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 003f0 001f0 001fe 000ff 000fe
Rank(1) Rlevel Rank 0x3, 0x00C5145147186145 : 5 5 5 5 7 6 6 5 5 (25)
Read ODT_CTL : 0x4 (60 ohms)
Rank(0) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 007f0 005f0 001fe 000fd 000fe
Rank(0) Rlevel Rank 0x3, 0x00C5145148186145 : 5 5 5 5 8 6 6 5 5 (47)
Rank(1) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 003f0 001f0 001ff 000fd 000fe
Rank(1) Rlevel Rank 0x3, 0x00C5145147186145 : 5 5 5 5 7 6 6 5 5 (31)
Read ODT_CTL : 0x3 (40 ohms)
Rank(0) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 003f0 001f0 001ff 000ff 000fe
Rank(0) Rlevel Rank 0x3, 0x00C5145147186145 : 5 5 5 5 7 6 6 5 5 (30)
Rank(1) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 003f0 001f0 001fc 000ff 000ff
Rank(1) Rlevel Rank 0x3, 0x00C5145147186145 : 5 5 5 5 7 6 6 5 5 (25)
Read ODT_CTL : 0x2 (30 ohms)
Rank(0) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 003f0 001f0 001ff 000ff 000fd
Rank(0) Rlevel Rank 0x3, 0x00C5145147186145 : 5 5 5 5 7 6 6 5 5 (36)
Rank(1) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 003f0 001f0 001ff 000ff 000fe
Rank(1) Rlevel Rank 0x3, 0x00C5145147186145 : 5 5 5 5 7 6 6 5 5 (30)
Read ODT_CTL : 0x1 (20 ohms)
Rank(0) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 003f0 00ff0 01fff 000ff 000fe
Rank(0) Rlevel Rank 0x3, 0x00C514514724A145 : 5 5 5 5 7 9 10 5 5 (200)
Rank(1) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 003f0 00ff0 01fff 000ff 000fc
Rank(1) Rlevel Rank 0x3, 0x00C514514724A145 : 5 5 5 5 7 9 10 5 5 (195)
Evaluating Read-Leveling Scoreboard.
RTT_NOM 0, 0, 0, 40 ohms : 0,0,0,3
RTT_WR 0, 0, 0, 0 ohms : 0,0,0,0
DIC 40, 40, 40, 40 ohms : 0,0,0,0
Read ODT_CTL : 0x5 (120 ohms)
Rank(0) Rlevel Rank 0x1, 0x0045145147186145 : 5 5 5 5 7 6 6 5 5 (30)
Rank(1) Rlevel Rank 0x1, 0x0045145147186145 : 5 5 5 5 7 6 6 5 5 (25)
DDR2T : 1
Performing software Write-Leveling
Rank(0) Wlevel Rank 0x1, 0x0000200000C62908 : 0(e) 0(e) 0(e) 0(e) 12 12 10 8 8
Rank(1) Wlevel Rank 0x1, 0x0000200000C62908 : 0(e) 0(e) 0(e) 0(e) 12 12 10 8 8
MODE32B : 1
LMC_INT : 0x00000000
N0.LMC0 Configuration Completed: 4096 MB
LMC Initialization complete. Total DRAM 4096 MB
Warning: Board descriptor tuple not found in eeprom, using defaults
EVB7000 board revision major:1, minor:0, serial #: unknown
OCTEON CN7130-AAP pass 1.2, Core clock: 1600 MHz, IO clock: 600 MHz, DDR clock: 667 MHz (1334 Mhz DDR)
Base DRAM address used by u-boot: 0x10fc00000, size: 0x400000
DRAM: 4 GiB
Clearing DRAM...... done
Hit any key to stop autoboot: 0
SF: Detected MX25L6433F with page size 256 Bytes, erase size 4 KiB, total 8 MiB
Found valid SPI bootloader at offset: 0x100000, size: 1596304 bytes
Loading bootloader from SPI offset 0x100000, size: 1596304 bytes
Warning: chips select 0 property cavium,t-wait, clocks 181, clock time 300, period 1666, mult: 1 exceeds maximum value 63, truncating.
Warning: chips select 1 property cavium,t-wait, clocks 181, clock time 300, period 1666, mult: 1 exceeds maximum value 63, truncating.
Warning: rd_delay 7 exceeds page time value 23 * multiplier 8
or rd_delay 7 exceeds read hold time 0 * multiplier 8
for chip select 1
U-Boot 2013.07 ACCTON Version 0.1.0.12 (Build time: Sep 15 2017 - 14:27:14)
Octeon unique ID: 0a8000104019f31e04c1
Using DRAM size from environment: 4096 MBytes
LMC0: Measured DDR clock: 666666211, cpu clock: 1600000000, ddr clocks: 111111373
SATA0: available
SATA BIST STATUS = 0x0
EVB7000 board revision major:1, minor:0, serial #:
OCTEON CN7130-AAP pass 1.2, Core clock: 1600 MHz, IO clock: 600 MHz, DDR clock: 667 MHz (1334 Mhz DDR)
Base DRAM address used by u-boot: 0x10f000000, size: 0x1000000
DRAM: 4 GiB
Clearing DRAM...... done
SF: Detected MX25L6433F with page size 256 Bytes, erase size 4 KiB, total 8 MiB
Flash: 0 Bytes
PCIe: Port 0 link active, 1 lanes, speed gen2
PCI console init succeeded, 1 consoles, 1024 bytes each
port 1 is not capable of FBS
port 1 is not capable of FBS
SATA#0
Net: octeon_eth_get_phy_info: Unknown PHY compatible string broadcom
octeth0, octrgmii0 [PRIME]
octeon_board_phy_init: Unknown PHY type broadcom for octrgmii0
Node 0 Interface 0 has 1 ports (RXAUI)
Node 0 Interface 2 has 4 ports (NPI)
Node 0 Interface 3 has 4 ports (LOOP)
Node 0 Interface 4 has 1 ports (AGL)
Type the command 'usb start' to scan for USB storage devices.
post boot function...
SPI boot index : 1
reset phy on CPLD!! ...
Hit any key to stop autoboot: 0