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Perhaps this was already answered previously but what's expected outcome of putting dual 385W CPU into LGA4677 SuperMicro dual-socket MB designed for 350W CPU (assuming I will dial-down frequency/cores via BIOS on a first boot). For instance there are plenty of Xeons having model number 84XXC (...

X13DEI has x16 RAM slots (x8 for each CPU), the reason I've described x16 ram sticks was to show that I have spares to try different combinations. Currently only one RAM stick is plugged in (and I've changed those several times for different module into right slot as per motherboard manual)...

Well, I've got LGA4677 MB a year ago and it still sits on a shelf because of most likely QS E3 stepping CPU is unstable (have ES D0 too but it doesn't even detect on SuperMicro), it keeps crashing every 2 hrs.. It might be something else though (have x16 different sticks of RAM, spare PSU) but...

For some reasons my regular non-overclocked single-rank DDR5 ECC RDIMM 16GB 4800 Micron (MTC10F1084S1RC48BA1 NGCC EC8 RDIMM DDR5 1RX8 - PC5-4800B-RD0-1010-XT) is flagged as hot by HWInfo64 even at temps above 35 ^C (this is under normal load, not stress-testing/benchmarking) despite Micron'...

Non-prod units (mostly ES but often even QS) are a lottery, I'm getting a lot of those (QAT, not DSA as per original post) with 8461V-QS despite latest drivers and all updates, although it might not be CPU but something else too.

Hello, Is there a way to increase delay PCIe devices enumeration step on Supermicro motherboards in BIOS initialization? ( I've X13DEI ) (A.K.A. step "94 PCI Bus Enumeration" ) I've a device (USB card) which has firmware most likely needing extra 5 seconds before reporting ready status back to...

Passive hubs (aka splitters) as mentioned above, for active devices google for "HW-585" - most popular cheap 3-channel controller (generates it's own PWM signal) with temp sensor there's also famous Corsair Commander with software managed via USB (includes RGB but this flashy stuff is mostly for...

IMV this "idle power" priority doesn't seem to be consistent with a very nature of high-core Server grade Xeon CPU concept on a first place. For low idle states there are desktop cpus and "efficiency" cores.

Has anyone tried if ASUS Z13PE-D16 support SPR D0 stepping? (and probably EMR ES/QS stepping flavours)

I was always updating firmware on both : IPMI (more specifically BMC) and BIOS - via WEB UI (including promoting into Golden Image on resiliency actions) checked couple of times SUM too since it was part of download but decided not to bother because it was much quicker via regular GUI.

Alibaba cloud is already running Emerald Rapids platform having 8575C cpus Here's sample bench with 4 CPU VM I'm still cautious about getting their older 8475B because of high possibility those having locked-out accelerators (via Intel's On Demand activation model), and still too high prices for...

Since it's still Sapphire Rapids then mine 8461V showing these memory results. Write and copy are a bit lower of course (around/below 200GB/s) P.S. screenshot from @JosefHrib above strangely shows worse speeds (except for L1/L2/L3 caches which are IMV a bit more important) despite having...

Agree, it's old stuff, SPR are the same (plus some server extra features hardly of any use for home/desktop customers) as 12th gen Core processors, e.g. i7-12700 - which on e-bay go at around $160 with 8 P-cores, therefore $20 per core, those do have higher frequencies so if we adjust price for...

So we're ending up with the conclusion that subset of AMX instructions is offloaded to TMUL which is implemented as separate accelerator (just like IAA/QAT/DLB/DSA) with unknown number of those AMX TMUL accelerator units on each CPU model (not being specified on Intel' Arc). I guess for now we...

Another related question - we have various Customer Sapphire Rapids custom CPU models spreading on a market, are those having extra features? or rather opposite - discounted result of failed binning with reduced functionality (e.g. AMX fails but CPUs can be used for Networking servers where this...

I'm actually getting confused, so are those TMUL(s?) per Core? or per CPU (like accelerator which would make more sense looking at documents above)? or per Chiplet (batch of cores - but this is less likely as I think it is a separate accelerator tile mounted on package assembly)? p.s. for sake...

Yes, they can send commands to TMUL accelerator, and have multiple first stage of AMX implementation tmm0...tmm[n-1] , but only one TMUL , therefore only one AMX (simply tmm commands will be waiting in queue for single TMUL) , right?

Any points to these facts? Not the AVX in general (which are indeed per core) but rather AVX-512 FMA ? (and AMX) Yes, Intel says here {Section called "Intel® Advanced Matrix Extensions (Intel® AMX)"} what AMX is actually Accelerator (of two components - second being TMUL) and architectural flow...

Is there a way to check number of AMX units available on Sapphire Rapids CPUs ? Like with AVX-512 FMA units - most CPUs have only two (even for higher-core CPU counts, e.g 48 cores and still only 2 AVX-512 FMA units, some less, some none) and similarly with other accelerators (QAT/DLB/DSA/IAA...

Another risk with e-bay purchases having controllers is about firmware - I've got two larger capacity Micron 3400 off the ebay a while ago, instantly tested and put on a shelf, recently time come to use those - system became unstable with frequent freezes in just 5-10 minutes of operations...