Intel's announcement does not explain clearly the purpose of these instruction-set architecture changes.
The purpose of APX is the increase of the number of general-purpose registers from 16 x 64 bit to 32 x 64 bit, aligning the Intel-AMD ISA with the competing ISAs, like ARM Aarch64, IBM POWER or RISC-V.
This is the third increase in size of the general-purpose register file since the launch of Intel 8086 in 1978, which had 8 x 16 bit registers, increased by 80386 in 1985 to 8 x 32 bit registers, then by AMD Opteron in 2003 to 16 x 64 bit registers.
Besides the main purpose, Intel has used this opportunity to add various improved instructions, among which there are 4 instructions that are inspired by instructions of ARM Aarch64, i.e. PUSH2 and POP2 (from store and load register pair of Aarch64), and CCMP and CTEST (from conditional comparison of Aarch64).
The purpose of AVX10 is to enable the introduction of CPUs that implement only a 256-bit subset of AVX-512, i.e. which have 256-bit vector registers and 32-bit mask registers.
After AMD has launched Zen 4, which supports AVX-512 in all products, Intel had to do something to remain competitive, despite their decision of using E-cores in most products, either alone, like in Alder Lake N or Sierra Forrest, or in combination with P-cores, like in Meteor Lake or Raptor Lake Refresh.
Because Intel continues to believe that implementing the full AVX-512 ISA is too expensive for their E-cores, they have settled on the solution of implementing a 256-bit subset of AVX-512 in all their future CPUs that are either hybrid or only with E-cores, presumably starting with those that will be launched in 2025.
Because most future Intel CPUs with AVX-512 will no longer support 512-bit registers and instructions, the name has become inappropriate, so AVX-512 has been rebranded as AVX10.
The first problem that had to be solved to enable a 256-bit subset of AVX-512 was how to identify this feature with CPUID.
Intel has used this opportunity to simplify considerably the identification of the available AVX-512 features with CPUID:
"As of future Intel Xeon processors with P-cores, code-named Granite Rapids, there are expected to be more than 20 discrete Intel AVX-512 feature flags.
To address this, Intel AVX10 introduces a new versioning approach to enumeration: a Vector ISA feature bit specifying Intel AVX10 support, an Intel AVX10 ISA Version Number, and three bits enumerating 128-, 256-, and 512-bit vector length support in the product.
The Intel AVX10 ISA Version Number will be inclusive and monotonically increasing. A developer can expect that Intel AVX10 Version N+1 will include all the features and capabilities included in Version N."
This new scheme will be applied starting with Granite Rapids and Granite Rapids D, whose AVX-512 ISA has been renamed as "AVX10.1".
The next version, "AVX10.2", which will be launched presumably in 2025, in the generation that will follow Granite Rapids, Granite Rapids D, Sierra Forrest, Grand Ridge, Arrow Lake, Arrow Lake S and Lunar Lake, will be the first version where most CPUs will implement the 256-bit subset of AVX-512.
The full AVX-512 ISA will continue to be supported only in the server CPUs that contain only P-cores, i.e. in the successors of Granite Rapids.
