I've been reading around this subject and I'm trying to figure something out.
My understanding that the L3 cache on Epyc Rome consists of 16MB of L3 cache per CCX, and there are 2xCCX-es per CCD.
Epyc 7402 has 24 cores, which implies 3x CCDs of 8 cores and 32MB of L3 cache each. Which would be fine except that adds up to 96MB of L3 cache and the spec says 128MB of L3 cache.
I can see only two possible explanations, both of which involve the presence of 4x CCDs on the 7402 CPU package. So either
1) each CCD has only 6 enabled CPU cores, or
2) there are three CCDs that are fully enabled and one CCD that only has the L3 cache enabled.
I think option 1) is more likely.
How thoroughly are the missing cores disabled? What are the chances of a BIOS edit being or a MSR setting, or soldering the missing SMD components on the bottom of the CPU getting the missing cores back online?
My understanding that the L3 cache on Epyc Rome consists of 16MB of L3 cache per CCX, and there are 2xCCX-es per CCD.
Epyc 7402 has 24 cores, which implies 3x CCDs of 8 cores and 32MB of L3 cache each. Which would be fine except that adds up to 96MB of L3 cache and the spec says 128MB of L3 cache.
I can see only two possible explanations, both of which involve the presence of 4x CCDs on the 7402 CPU package. So either
1) each CCD has only 6 enabled CPU cores, or
2) there are three CCDs that are fully enabled and one CCD that only has the L3 cache enabled.
I think option 1) is more likely.
How thoroughly are the missing cores disabled? What are the chances of a BIOS edit being or a MSR setting, or soldering the missing SMD components on the bottom of the CPU getting the missing cores back online?