ElI5 - Why would CXL "replace" Optane/3D-Xpoint?

[NablaSquaredG]

Although the pmem was based on DDR4 protocol, there may be a reason why this thing can't run on any platform other than Xeon Scalable. More specifically, first gen DCPM can only run on 2nd gen Xeon scalable and 2nd gen DCPM can only run on 3rd gen, no cross compatibility at all even for engineering samples. Intel's new IMCs may have some proprietary designes specifically for DCPM.

There are limitations imposed on how far Intel can diverge from the standard DDR4 specs by the fact that you can have DCPMM + regular DRAM on the same channel

 

[111alan]

There are limitations imposed on how far Intel can diverge from the standard DDR4 specs by the fact that you can have DCPMM + regular DRAM on the same channel

There are things like MRDIMM and MCRDIMM which can already double the bandwidth. There are also some kind of memory expansion board used on old E7 CPUs and some other tech I can't remember the name of which can also increase the bandwidth per slot. I think the room for optimization is pretty big for DDR slots.

BTW this result isn't cheated with hidden cache. With IOmeter which tests the entirety of the drive, one DCPMM can also reach 40GB/s by itself. But it needs multiple CPU threads to do so, there are still some strange designs in there.

 

[BoredSysadmin]

While interesting findings, accurate or not, isn't DDR5-8000 should be able to reach 64GB/s

 

[Patrick]

Just to be clear, DCPMM did have special memory controller features to make it work which is why it was only Xeon Scalable

 

[NablaSquaredG]

Just to be clear, DCPMM did have special memory controller features to make it work which is why it was only Xeon Scalable

Then would you mind sharing how Intel would be able to overcome the 21333.33MB/s peak transfer rate of a single DDR4 channel?