CPU Cache

[T_Minus]

Is there a technical reason why lower end Intel Xeons don't have as much cache as their high core brothers and sisters? Does the extra cache not help w/out the cores to process the data?


E5-2699 v3 = 45MB (18 Core)
[URL='http://ark.intel.com/products/85765/Intel-Xeon-Processor-E5-4667-v3-40M-Cache-2_00-GHz']E5-4667 V3 = 40MB (16 Core)[/URL]
E5-2660 v3 = 25MB (10 Core)
E5-2620 V3 = 15MB (6 Core)
E5-1650 V3 = 15MB (6 Core)
E5-1680 V3 = 20MB (8 Core)

 

[Quasduco]

Unless my math is faulty, they each have 2.5MB per core, high end or low end...
Just put the numbers in a spreadsheet, too. 2.5MB per core on all models you listed...

 

[T_Minus]

Why can't we have 45MB cache with 6 cores?

Is it not beneficial?

 

[Patriot]

There are three dies configurations typically... so you would never have the HCC die with only 1/3rd working cores... cache is also expensive in die space and... $$$ probably wouldn't improve the performance enough to justify the costs....
That said I have some hex core 4p v2 chips that have more cache than they should, as they are 12c die chips. Id imagine for very very specific database scenarios they might be good... but I would rather all the cores.

 

[Diavuno]

Last I heard from an Intel employee (back in the Core 2 days) it has to do with manufacturing, some chips are made with 8 mb, but some of it tests bad, so they disable the bad sections and round it to the next number the CPU is designed to work with.

with modern chips and L3 shared it probably has to do with that and/or the cost of wafers.

 

[T_Minus]

There are three dies configurations typically... so you would never have the HCC die with only 1/3rd working cores... cache is also expensive in die space and... $$$ probably wouldn't improve the performance enough to justify the costs....
That said I have some hex core 4p v2 chips that have more cache than they should, as they are 12c die chips. Id imagine for very very specific database scenarios they might be good... but I would rather all the cores.

It would be impossible, the very cache are not just mere cache but explicitly placed right next to every core.

Adding more cache will fail as it's too far from core itself (physics)

So, what about ES chips? I have some 12C that show 14 Temp sensors, they're ES.

It sounds like it would be impossible to have more cache since they're tied directly to the core? So if the core is disabled so is the cache?

 

[Aluminum]

So yeah, you guys don't look at ark enough, 'cause you're kinda wrong

I'm not sure how, but some xeons DO have more L3 cache than the 2.5MB/core, they've been doing it as far back as Ivy Bridge.

If I had to guess, this "extra" cache can't cross one of the rings on the MCC/HCC dies, but only intel really knows. Here is a recent 6 core with 30MB lol! Perhaps its a 12 core with every other one disabled and using the cache of the core nearest to it, 3 active cores per ring? Pretty weird but there you go.

 

[Aluminum]

BTW, this site like to make lots of crap up but this came from an intel doc; a nice logical diagram of E5 cores, only intel really knows the physical layout.

 

[Diavuno]

It would be impossible, the very cache are not just mere cache but explicitly placed right next to every core.

Adding more cache will fail as it's too far from core itself (physics)

Only L1 and L2.

L3 is a shared blob.

 

[Patriot]

BTW, this site like to make lots of crap up but this came from an intel doc; a nice logical diagram of E5 cores, only intel really knows the physical layout.

Yes, and Intel's own documentation is not always accurate. We also have no idea how they harvested cores on the MCC die to have 30MB of working L3.

 

[Aluminum]

Yes, and Intel's own documentation is not always accurate.

Ugh yeah, I still want a refund for my E3-1265Lv2 that supposedly came with a HD4000 gpu as I wanted it for a fanless HTPC and it was big bucks back then. A few months later "oopsies" ark mysteriously updated it to the correct and even weaker 2500 gpu which explains some of the trouble it had with harder 1080p decodes.

At least I didn't get burned by the TSX-NI crap, they also listed AES-NI support wrong for a couple low-end models for a long time.

Its like every time they screw up they get a bigger and bigger pass, back in the PDIV days at least eventually it was "sorry, heres your new cpu" by the time of the Series 6 SATA debacle it was "talk to your OEM" and lately its "the errata has been updated, pray we don't update it further". ****ing de-facto monopoly, sigh.