I'd imagine the chiplets will be the same as that's one of the biggest benefits to NOT using a monolithic die for Ryzen. By sharing the same chiplet, the sellable yields will be higher. Chips not suitable for Epyc can be brought down the stack and pushed via Ryzen sales.
That is in exchange of a latency increase because now the CPU chiplet has to go through the I/O die, whereas previously they were a single die. It also makes the package more complex and expensive, but I don't know by how much and how economy of scale would make that look against whatever they're gaining on die efficiency. For big things like Rome it makes sense, for AM4 Ryzens and APUs... I'l prefer to wait benchmarks.
I'm still skeptical about this approach, there should be some edge cases with regressions due to the increased latency. Alas, for people that now know that an 16C AM4 Ryzen is possible, they are going to be very happy either way.
Also, do we know already if the CPU CCX concept still exist or at least we can count on that the intradie chiplet latency is uniform?