Recent content by Bronek

FWIW I just tested various enlightenments on windows 10 and settled on <features> <acpi/> <apic/> <pae/> <hyperv mode='custom'> <relaxed state='on'/> <vapic state='on'/> <spinlocks state='on' retries='4096'/> <vpindex state='on'/> <runtime...

Yeah I might be missing some hyperv enlightenment. I use almost identical XML for my Linux machines and they do not benefit from those, so I never bothered.

As for cache='directsync' , I am changing it to cache='none' for consistency, someone else would probably start with "none". In my case it probably makes no difference since my storage is ZFS volume (aka "zvol") which is always cached because ZFS forces caching. I think "none" and "directsync"...

PS lstopo --filter icache:none --whole-io is your friend ;)

Sure. This one is for a Windows guest. You need to compare this against lstopo output for this socket, see graphics. Basically, since I'm passing three devices (PCI 24 and 26 are USB card, while PCI 01 is a NVIDIA GPU) and they are attached to two different dies of the EPYC CPU, I've decided to...

I've managed to significantly cut down interrupt latency by changing CPU pining vs CPU isolation of the host. It's not the same as with VAPIC, but close (judging by ḣow rare are the occurrences of sound artifacts)

We are talking about EFI BIOS of the motherboard, so that would be something that Gigabyte or AMI can provide me, right? Or should I just look in Custom UEFI/BIOS - Aptio & AMBIOS ?

For the curious, Gigabyte support answered my question what's wrong with avic on this motherboard. Honestly, I do not quite understand the answer and have asked for clarification.

To answer my own question, now that I have replaced the motherboard with MZ72-HB0 rev 3.0 - by default, avic feature is disabled on this motherboard as well. Given that it works on Rome, perhaps it's a CPU problem? This is very curious, I am yet to find a motherboard which does not disable this...

Not sure how they could help? Or do you mean ask if I can get this feature on Asrock ROME2D16?

@mirrormax setting up virtual interrupt controller on AMD is non-trivial, see the instructions at SVM AVIC/IOMMU AVIC improves interrupt performance on Zen(+)/2/etc based processors ; BTW this is when I learned that my CPU (and as later turned out - motherboard actually) does not support AVIC.

@mirrormax thank you, this is good to see. Hope someone with Milan will report as well.

Yeah good question - I have no idea. I know (from https://www.amd.com/system/files/TechDocs/56683-PUB_1.04.pdf , page 40) that AVIC is disabled when SEV-SNP is enabled and there are some other potential issues related e.g. pages 52, 56, 58 , but this is an old CPU feature. It should work for...

Wow, I never used this kind of BIOS explorer. Very impressive. Still, I need to know if some user of this particular motherboard and a CPU from the Milan family can see the avic feature listed in the CPU flags. My Supermicro is disabling it :(

Can some user of MZ72-HB0 motherboard verify that this motherboard is not disabling Virtual Interrupt Controller (ie. avic) feature of an EPYC 7003 CPU? Turns out that the Supermicro H12DSi-N6 which I am using now is disabling this feature (...