According to very old Roadmaps, the successor to EPYC Embedded 3000 series based on first generation Zen, was slated for Q2 2020, and we're getting close to that quarter, yet we have no recent info.
I have a bit of an issue with the Zen 2 EPYC Embedded codename, since those Roadmaps named it Starship whereas The Stilt and some other sources seems to point out that Starship is an old codename remant used by AMD for a 48C Zen 2 Processor that got scrapped in favour of Rome (Or for Zen 2 itself? I don't have it very clear, to be honest). These roadmaps were from BEFORE the original Ryzen release.
The reason why I'm extremely interesed in EPYC Embedded is because I hate Socket AM4, for the reasons listed here. Basially, Socket AM4 exposes an inferior feature set than what the Zen die actually has on it, and which is fully exposed in the EPYC Embedded line, as:
- Zen has a total of 32 PCIe Lanes, but Socket AM4 only exposes 24, 8 less. Single Die EPYC Embedded parts exposes the full 32 set.
- Zen can work in full SoC mode with no Chipset, as proven by EPYC Embedded. In Socket AM4, 4 PCIe Lanes are required for the Chipset, which is a glorified PCIe Switch, SATA and USB Controller, leaving only 20 for direct Processor connectivity. An alternative was to use the A300/X300 "Chipsets", which are simply a sort of security Coprocessor wired to Zen via the SPI Bus, freeing the 4 Lanes. However, EPYC Embedded doesn't need anything like that at all, saving both real state on the Motherboard and Chipset cost.
- Some of the extra PCIe Lanes are muxed to other builtin controllers, significantly reducing the need for Chipset Port fanout. Besides PCIe, on EPYC Embedded you can get 8 SATA and 4 10G MACs (Albeit I'm not sure on the possible combinations, as lack of documentation means that I don't know whenever the secondary 16x PCIe Controller can do 4 PCIe + 8 SATA + 4 10G MAC, or just 8 PCIe + 4 SATA + 4 10G MAC, as if the 10G MACs and half of the SATAs were multiplexed on the same lanes). Socket AM4 instead only allows for 2 of the builtin SATAs.
- Zen supports all the cast of DDR4 variants, including UDIMM, UDIMM w/ECC, RDIMM and RDIMM w/ECC, and I'm sure than LRDIMM. Socket AM4 doesn't support any type of RDIMM, and ECC support is unofficial for the most part.
- Being soldered means that it doesn't require a ZIF type Socket, which as far that I know is a rather expensive part on a Motherboard BoM.
- At release, there was a price parity between similarily geared parts like the EPYC Embedded 3251 and the Ryzen 1700, so in a direct Processor comparison, the EPYC Embedded always won in features.
The cons are as followings:
- Zen SoC has only 4 USB Ports, which is just TOO FEW for consumer user. Heck, even Supermicro mITX Motherboarsd with EPYC Embedded intended for Servers had a few USB Hubs to provide more onboard Ports. This is perhaps most important issue about EPYC Embedded for consumer, as you're forced to use an USB Hub or PCIe USB Controller to add more Ports.
- The clock speed is around a full GHz lower on EPYC Embedded than similar consumer Socket AM4 parts, albeit that would make any possible overclocking more interesing.
- Being soldered, if you want to upgrade the Processor, you have to replace the Motherboard, too.
- Being soldered, it doesn't uses standard Heatsinks, it needs custom, unupgradeable cooling solutions (Unless there is any sort of standard for them). This means that overclocking will be limited. Same with VRM designs being aimed at the soldered Processor TDP and not having tons of headroom.
- EPYC Embedded is already two generations old compared to all the other lines, since it was released when Zen was still the latest, but it missed Zen+, and is still waiting for the Zen 2 refresh.
My original idea is that a Zen SoC based platform aimed at consumers would be far better than traditional Socket AM4, more so with its mITX attempts like the AsRock DeskMini A300, which an embedded version like the Ryzen Embedded V1000 would do much better. I still believe that Zen as a SoC would be overally a much better product, as many consumer use cases can get by with the Zen SoC I/O without requiring a Chipset for further fanout, as, with the exception of the USB Ports. It would greatly simplify the platform to kick the Chipset out. Besides, most users don't upgrade often, so they don't lose a lot by going soldered.
Going back to Zen 2, based on how much AMD likes to reuse designs and silicon since Zen, I would be led to believe that a Zen 2 EPYC Embedded should be directly based on Matisse. Mattise is radically different to older Summit Ridge and Pinnacle Ridges due to its MCM design, and specifically, because the IO die is the same than the AMD X570 Chipset, which provides a heavy set of I/O including a ton of SATA and USB Ports. The latter would fix what I considered the worst shortcoming of Zen as a SoC.
Since Socket AM4 has to be backwards compatible, its pinout set in stone, so AMD can't exploit the extra connectivity in the I/O die, but this is not the case for the embedded variants. As such, there is the mythical question about what features are removed, or increased, in the IO die compared to the previous Zen SoC, as we know just what AMD tell us. I mean, that the Zen SoC had integrated 10G MACs was a surprise when AMD announced EPYC Embedded, they NEVER mentioned it at any point before, so there can be a lot of surprises in that already-released piece of silicon.
According to these slides, the X570 Chipset has at least 16 PCIe Lanes, of which 8 can be used for SATA, 4 more PCIe Lanes for the uplink with Socket AM4, 4 dedicated SATA, 8 USB 3.1 Ports, and 4 USB 2.0 (XHCI based?) Ports. Actually, just by the 24 PCIe Lanes required in AM4 to maintain backwards compatibility, the math doesn't add up, so in Chipset format, the IO die is exposing LESS PCIe Lanes than as part of a Zen 2 Processor!
Moreover, there is no info about whenever AMD will keep the 10G MACs or not. Somehow I believe that AMD keeped them in the Matisse IO die, since EPYC Embedded is being used in COM Express Type 7 boards, and Type 7 has room for 32 PCIe Lanes and 4 10GBASE-KR links. To not include that much IO, will be a step backwards as a Zen 2 EPYC Embedded would not be able to cover the use cases of the current Zen based one.
What I do believe, is that since Matisse can scale up to 16C with a single IO die, that the Dual Die EPYC Embedded may possibly be phased out, as these maxed out at 16C, too, but with twice the Memory Channels and PCIe Lanes. If anything, the Dual Die EPYC Embedded should be replaced by a much bigger Rome based one, assuming that AMD wants to do that. At least based on the products I saw, the Dual Die version is extremely rare in the wild, so it would not be surprising.
Renoir for Ryzen Embedded series is as interesing, or perhaps more so, than Matisse, but I don't think that given its mobile focus, AMD dumped a lot of dark silicon for IO that will be used in a niche product still far away.
I have a bit of an issue with the Zen 2 EPYC Embedded codename, since those Roadmaps named it Starship whereas The Stilt and some other sources seems to point out that Starship is an old codename remant used by AMD for a 48C Zen 2 Processor that got scrapped in favour of Rome (Or for Zen 2 itself? I don't have it very clear, to be honest). These roadmaps were from BEFORE the original Ryzen release.
The reason why I'm extremely interesed in EPYC Embedded is because I hate Socket AM4, for the reasons listed here. Basially, Socket AM4 exposes an inferior feature set than what the Zen die actually has on it, and which is fully exposed in the EPYC Embedded line, as:
- Zen has a total of 32 PCIe Lanes, but Socket AM4 only exposes 24, 8 less. Single Die EPYC Embedded parts exposes the full 32 set.
- Zen can work in full SoC mode with no Chipset, as proven by EPYC Embedded. In Socket AM4, 4 PCIe Lanes are required for the Chipset, which is a glorified PCIe Switch, SATA and USB Controller, leaving only 20 for direct Processor connectivity. An alternative was to use the A300/X300 "Chipsets", which are simply a sort of security Coprocessor wired to Zen via the SPI Bus, freeing the 4 Lanes. However, EPYC Embedded doesn't need anything like that at all, saving both real state on the Motherboard and Chipset cost.
- Some of the extra PCIe Lanes are muxed to other builtin controllers, significantly reducing the need for Chipset Port fanout. Besides PCIe, on EPYC Embedded you can get 8 SATA and 4 10G MACs (Albeit I'm not sure on the possible combinations, as lack of documentation means that I don't know whenever the secondary 16x PCIe Controller can do 4 PCIe + 8 SATA + 4 10G MAC, or just 8 PCIe + 4 SATA + 4 10G MAC, as if the 10G MACs and half of the SATAs were multiplexed on the same lanes). Socket AM4 instead only allows for 2 of the builtin SATAs.
- Zen supports all the cast of DDR4 variants, including UDIMM, UDIMM w/ECC, RDIMM and RDIMM w/ECC, and I'm sure than LRDIMM. Socket AM4 doesn't support any type of RDIMM, and ECC support is unofficial for the most part.
- Being soldered means that it doesn't require a ZIF type Socket, which as far that I know is a rather expensive part on a Motherboard BoM.
- At release, there was a price parity between similarily geared parts like the EPYC Embedded 3251 and the Ryzen 1700, so in a direct Processor comparison, the EPYC Embedded always won in features.
The cons are as followings:
- Zen SoC has only 4 USB Ports, which is just TOO FEW for consumer user. Heck, even Supermicro mITX Motherboarsd with EPYC Embedded intended for Servers had a few USB Hubs to provide more onboard Ports. This is perhaps most important issue about EPYC Embedded for consumer, as you're forced to use an USB Hub or PCIe USB Controller to add more Ports.
- The clock speed is around a full GHz lower on EPYC Embedded than similar consumer Socket AM4 parts, albeit that would make any possible overclocking more interesing.
- Being soldered, if you want to upgrade the Processor, you have to replace the Motherboard, too.
- Being soldered, it doesn't uses standard Heatsinks, it needs custom, unupgradeable cooling solutions (Unless there is any sort of standard for them). This means that overclocking will be limited. Same with VRM designs being aimed at the soldered Processor TDP and not having tons of headroom.
- EPYC Embedded is already two generations old compared to all the other lines, since it was released when Zen was still the latest, but it missed Zen+, and is still waiting for the Zen 2 refresh.
My original idea is that a Zen SoC based platform aimed at consumers would be far better than traditional Socket AM4, more so with its mITX attempts like the AsRock DeskMini A300, which an embedded version like the Ryzen Embedded V1000 would do much better. I still believe that Zen as a SoC would be overally a much better product, as many consumer use cases can get by with the Zen SoC I/O without requiring a Chipset for further fanout, as, with the exception of the USB Ports. It would greatly simplify the platform to kick the Chipset out. Besides, most users don't upgrade often, so they don't lose a lot by going soldered.
Going back to Zen 2, based on how much AMD likes to reuse designs and silicon since Zen, I would be led to believe that a Zen 2 EPYC Embedded should be directly based on Matisse. Mattise is radically different to older Summit Ridge and Pinnacle Ridges due to its MCM design, and specifically, because the IO die is the same than the AMD X570 Chipset, which provides a heavy set of I/O including a ton of SATA and USB Ports. The latter would fix what I considered the worst shortcoming of Zen as a SoC.
Since Socket AM4 has to be backwards compatible, its pinout set in stone, so AMD can't exploit the extra connectivity in the I/O die, but this is not the case for the embedded variants. As such, there is the mythical question about what features are removed, or increased, in the IO die compared to the previous Zen SoC, as we know just what AMD tell us. I mean, that the Zen SoC had integrated 10G MACs was a surprise when AMD announced EPYC Embedded, they NEVER mentioned it at any point before, so there can be a lot of surprises in that already-released piece of silicon.
According to these slides, the X570 Chipset has at least 16 PCIe Lanes, of which 8 can be used for SATA, 4 more PCIe Lanes for the uplink with Socket AM4, 4 dedicated SATA, 8 USB 3.1 Ports, and 4 USB 2.0 (XHCI based?) Ports. Actually, just by the 24 PCIe Lanes required in AM4 to maintain backwards compatibility, the math doesn't add up, so in Chipset format, the IO die is exposing LESS PCIe Lanes than as part of a Zen 2 Processor!
Moreover, there is no info about whenever AMD will keep the 10G MACs or not. Somehow I believe that AMD keeped them in the Matisse IO die, since EPYC Embedded is being used in COM Express Type 7 boards, and Type 7 has room for 32 PCIe Lanes and 4 10GBASE-KR links. To not include that much IO, will be a step backwards as a Zen 2 EPYC Embedded would not be able to cover the use cases of the current Zen based one.
What I do believe, is that since Matisse can scale up to 16C with a single IO die, that the Dual Die EPYC Embedded may possibly be phased out, as these maxed out at 16C, too, but with twice the Memory Channels and PCIe Lanes. If anything, the Dual Die EPYC Embedded should be replaced by a much bigger Rome based one, assuming that AMD wants to do that. At least based on the products I saw, the Dual Die version is extremely rare in the wild, so it would not be surprising.
Renoir for Ryzen Embedded series is as interesing, or perhaps more so, than Matisse, but I don't think that given its mobile focus, AMD dumped a lot of dark silicon for IO that will be used in a niche product still far away.
