You need to look at CPU 0 not 1 for single CPU
You need to look at CPU 0 not 1 for single CPU
Yeah - the used CPU market for SP is not good to start with - thats not going to end well (cheap)I'm in too with few probably. I bet they dump it for the older v3-v4 systems because of Scalable Xeons crazy prices. And now we face it
Got you. I didn't realise there was any flexibility with the mapping - I assumed it was fixed 1:3Yes I know, but is a 12:4 oversubcription necessary or would 12:2 suffice? And this is a PLX chip so does it actually get impacted by oversubscription?
Yes, that's correct. That block diagram only shows the onboard NVMe though (2 per proc). For this, 2 risers are used with 4 NVMe ports each which are multiplied to 12 each in the backplanewith 1 CPU you get 12x NVMe port usable. Right ?
Here you go@zeynel did your barebone arrive yet?
Could you post some pictures of the riser cards or wich model it came with.
It was my first experience with ultra servers and the only issues were backplane powering cable for 2U chassis I mentioned earlier and few MB mounting points you need to move or apply custom spacer to fit X11DPU inside 1U. Don't forget about FANs to be replaced as well.So, all feedbacks are good ?
This box is very attractive (except costly scalable cpus) !
@Iaroslav, switching with the X10DRU-i+ was a pain or it was quite simple ?
That's maybe possible, as SC819UTS-R1K02P-A mentioned for H12DSU-iN | Motherboards | Super Micro Computer, Inc. also present in optimized chassis for X11DPU-XLL | Motherboards | Products | Super Micro Computer, Inc.On the different end of the MB side, does anyone know if the H11DSU-iN or H12DSU-iN would work with this case along with an AOC-SLG3-8E2P HH NVMe HBA? Would be great to try this with Epyc Rome ES CPUs