Hi,
Genoa will increase memory channels from 8 -> 12 (matching core count growth, disclosed in the recent AMD Financial Analyst Day). Current 2 socket x 16 DIMM slots already fill the width of standard 19" chassis (or 8 DIMMS per socket in 2U4N configurations). Where are the additional DIMM slots going to physically fit? Power per socket is also increasing, are we moving towards single socket servers?
Cheers, Y0s
Genoa will increase memory channels from 8 -> 12 (matching core count growth, disclosed in the recent AMD Financial Analyst Day). Current 2 socket x 16 DIMM slots already fill the width of standard 19" chassis (or 8 DIMMS per socket in 2U4N configurations). Where are the additional DIMM slots going to physically fit? Power per socket is also increasing, are we moving towards single socket servers?
Cheers, Y0s