Got my self hands on a Asrock X570D4U board with a Ryzen 5 3600 CPU and attached some peripherals to it:
M2 slot filled with PCIE3.0x4 NVME SSD
PCIE4 slot filled with Intel X520-2DA (dual 10gbits NIC) PCIE2.0x8
PCIE6 slot filled with a SAS 3008 PCIE3.0x4, hooked up only 4 SATA disks (for now)
Now the thing is that I see that the SAS 3008 only runs on PCIE3.0 with x4 lanes (downgraded) and not on a x8 lanes bandwidth as according to the SAS 3008 chipset datasheet.
If I count up all the PCIE lanes and knowing that the Ryzen 5 3600 has 24 PCIE lanes to distribute:
x8 for Intel NIC
x4 for M2 SSD
x4 for the Upstream link X570 chipset
I still have x8 lanes left for the SAS controller. Why is it only taking (downgrade) to x4? Swapping the SAS 3008 from PCIE slot 4 to Slot 6 does not make any difference.
If I remove the Intel NIC board completely, still the SAS 3008 on x4 lanes.
Thanks for some explanation/insights you could give me.
Dump of the lspci -vv
2d:00.0 Serial Attached SCSI controller: Broadcom / LSI SAS3008 PCI-Express Fusion-MPT SAS-3 (rev 02)
Subsystem: Broadcom / LSI SAS9300-8i
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 61
IOMMU group: 28
Region 0: I/O ports at f000 [disabled]
Region 1: Memory at fc540000 (64-bit, non-prefetchable) [size=64K]
Region 3: Memory at fc500000 (64-bit, non-prefetchable) [size=256K]
Expansion ROM at fc400000 [disabled] [size=1M]
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [68] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 4096 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0.000W
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset-
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 8GT/s, Width x8, ASPM not supported
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 8GT/s (ok), Width x4 (downgraded)
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
M2 slot filled with PCIE3.0x4 NVME SSD
PCIE4 slot filled with Intel X520-2DA (dual 10gbits NIC) PCIE2.0x8
PCIE6 slot filled with a SAS 3008 PCIE3.0x4, hooked up only 4 SATA disks (for now)
Now the thing is that I see that the SAS 3008 only runs on PCIE3.0 with x4 lanes (downgraded) and not on a x8 lanes bandwidth as according to the SAS 3008 chipset datasheet.
If I count up all the PCIE lanes and knowing that the Ryzen 5 3600 has 24 PCIE lanes to distribute:
x8 for Intel NIC
x4 for M2 SSD
x4 for the Upstream link X570 chipset
I still have x8 lanes left for the SAS controller. Why is it only taking (downgrade) to x4? Swapping the SAS 3008 from PCIE slot 4 to Slot 6 does not make any difference.
If I remove the Intel NIC board completely, still the SAS 3008 on x4 lanes.
Thanks for some explanation/insights you could give me.
Dump of the lspci -vv
2d:00.0 Serial Attached SCSI controller: Broadcom / LSI SAS3008 PCI-Express Fusion-MPT SAS-3 (rev 02)
Subsystem: Broadcom / LSI SAS9300-8i
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 61
IOMMU group: 28
Region 0: I/O ports at f000 [disabled]
Region 1: Memory at fc540000 (64-bit, non-prefetchable) [size=64K]
Region 3: Memory at fc500000 (64-bit, non-prefetchable) [size=256K]
Expansion ROM at fc400000 [disabled] [size=1M]
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [68] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 4096 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0.000W
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset-
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 8GT/s, Width x8, ASPM not supported
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 8GT/s (ok), Width x4 (downgraded)
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
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