Microchip SMC 1000 For The Serial Attached Memory Future

Discussion in 'STH Main Site Posts' started by Patrick Kennedy, Aug 5, 2019.

  1. #1
    Blinky 42 and William like this.
  2. marcoi

    marcoi Well-Known Member

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    That's some cool tech.
     
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  3. ATS

    ATS Member

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    Lets see, higher latency than FB-DIMM, same or higher power... Don't really see this ever really being used. Nor do I see the pie in the sky dis-aggregation ever happening for performance, power, and cost reasons. HPE et al want it because it is a high value add for them that they can overcharge for, but it really doesn't do anything for the actual customer and can only exist in a world where things like latency don't exist.
     
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  4. gigatexal

    gigatexal I'm here to learn

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    So the mainframe design is coming to servers? What’s old is new again: disaggregated chips I guess could work. I do like the interface design of making the chip not know what kind of memory it’s talking to just that it is. That’s very software centric.
     
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  5. ATS

    ATS Member

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    A lot of these proposals are software centric and completely oblivious to hardware. So, you are going to disaggregate? That means you are going to need a fairly high radix switch between memory and compute. Which means the latency through that switch is going to be measured in 10s to 100s of nS. You've now at least doubled memory latency.

    The problem is its not disaggregation but basically reinventing the UE10k with all of its costs for effectively zero benefit since all the software you are going to be running on top of the beast is perfectly happy running on 1-2P servers communicating over ethernet. The industry already tried the UE10k 15+ years ago and moved on to much cheaper and more efficient machines.
     
    #5
    gigatexal likes this.
  6. gigatexal

    gigatexal I'm here to learn

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    Yeah I don’t know any of the history. I just have a cursory understanding of how the big IBM mainframes are setup with their multiple systems each with brains unto themselves to handle things. That’s what the article sounded like or how the FPU began as a distinct unit and then migrated onto the chip and the same with the memory controller with the Opteron line and now it seems things are disaggregating to be more mainframe like.
     
    #6
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