I'm familiar with typical FC-BGA substrate materials and associated fabrication processes. I have not cross sectioned a finished LGA-3647 package to verify construction, but it will likely be a 400~600µm core (which provides the base "rigidity" for the substrate) with 4~8 build up layers per side.
Each of those build up layers is essentially a laminated resin "film" (25~35µm thick) with very fine Cu traces. The smallest traces (typically on the layers closer to the die due to routing density requirements) could be <10µm line/space. The surface of the resin is roughened prior to Cu deposition, (it the order of unit µm), but the Cu traces have limited adhesion to the resin. (for reference, an average human hair is in the range of 50~60µm)
Modern CPU's are incredibly resilient, and it amazes me that they survive the abuse (static, thermal, mechanical) that they do, thankfully the modern fabrication and test processes have improved reliability significantly over the years.
However, given the large visible crack in the solder mask at the LGA interface, it looks as if there has been substantial mechanical stress applied to the package. It wouldn't matter to me if these were signal or power pads, this is a compromised device, I personally wouldn't waste my time on it.
Loads of technical information available on substrate fabrication, design, test methods for those who may be interested...
Ajinomoto (yes, the food/biotech guys) provide the industry with the build up film. See
this link for an overview of their Electronic Materials, and
this link for a paper that describes the high level fabrication methods.
John Lau is one of the IC Packaging industry gurus,
this paper and
this paper contain cross sections of the typical internal package constructions.
