Thought about this several days ago, forgot to update. The distance between dies are a little too long for an EMIB bridge. I remember CPX-AP isn't canceled though, rather it's an OEM-only config. Seems that Facebook is using this kind of things.LGA4677 has a considerably different layout though (See attached diagrams - src: diagrams on imgur extracted from TE's documentation).
Those extra pads (The smaller, circular ones) are not primary data or power pads, but are used for auxiliary/debug functionality, such as fine-grained input power tuning, QC, or debugging. Intel does not include those pads in the LGA designation - only the primary pads.
IF this is sapphire rapids, it could be a very early sample not designed for production use, or for a specialized platform, however I strongly suspect this is not the case.
Rather, I think its probable that this is one of the MCM cooperlake chips (up to 56c per socket on the whitley platform) that was supposed to launch early this year but were suddenly canceled. Other known examples of cooperlake ES chips have those extra pads, both on cedar & whitley. The attached photos are of a cedar isles platform cooperlake xeon ES that was delidded (src: bilibili user yuuki_ans via leak finder momomo_us on twitter). Note that it too has all those extra pads.
QTL1 is cooper. there are ice lake ES1 with QSxx(early 2019) and QUxxLooks so. Also just noticed the QDF starts with QT, maybe an Icelake ES1.
Never know why they have two different 4189 sockets. Think the reason may be UPI/PCI-e pin distribution.QTL1 is cooper. there are ice lake ES1 with QSxx(early 2019) and QUxx
i was wrong. seems intel made cooper for socket P4 first and changed later to P5.
QTQ2 = Cooper Lake-SP ES1, 32c(2x16C), 44M, 250W
first the sockets are same. at both cooper and ice should run in same motherboards.Never know why they have two different 4189 sockets. Think the reason may be UPI/PCI-e pin distribution.