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Lenovo Thinkcentre/ThinkStation Tiny (Project TinyMiniMicro) Reference Thread

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WifiCable

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Dec 18, 2023
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wait so lemme understand this correctly - i have a p3 tiny gen 1 and previously i couldn't get any output signal fr an LP RX 6400 (pcie x4) but managed to get a Radeon wx 3200 (pcie x8) to work

I can just... cover the specified pad on my CPU with a piece of tape and potentially 'undo' lane reversal, which essentially prevents me from using anything other than pcie x8 or x16? I might give this a try if I can find some time this wknd
Yes, in theory just covering that pad on the CPU should fix this issue for you and make the RX 6400 work. I'd love to hear back if it works on your machine!
 

besseddrest

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May 14, 2025
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Yes, in theory just covering that pad on the CPU should fix this issue for you and make the RX 6400 work. I'd love to hear back if it works on your machine!
just need to know what i risk, though i think this is harmless if i'm careful

is there any specific kind of tape I should use, or should avoid?
 

WifiCable

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just need to know what i risk, though i think this is harmless if i'm careful

is there any specific kind of tape I should use, or should avoid?
As far as I can tell it should be entirely harmless yeah, unless you use some kind of cursed tape that fuses the CPU to the socket or something lol. My first choice would be a tiny piece of kapton tape, but in absence of that I wouldn't feel uncomfortable using regular everyday tape either, as long as it's thin, electrically insulating, and doesn't stick like glue.
Do keep in mind the diagram I showed is from the perspective of looking down at the socket, not the CPU. But even if you cover the wrong pad I can't think of any way that could cause permanent damage. Just in case though, I can't be held responsible for whatever happens, but I would never wish harm on a Tiny, I love the things. I would test this on my own unit in a heartbeat, if I had one.
 

jlist

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Jan 22, 2024
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just need to know what i risk, though i think this is harmless if i'm careful

is there any specific kind of tape I should use, or should avoid?
I remember the tape mod (aka the LGA775 BSEL mod) done to CPUs 15+ years ago were mostly performed using regular black electrical tape. I guess since the pads have gotten smaller and closer now, you should be careful to not cover any adjacent pins.
 

besseddrest

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May 14, 2025
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As far as I can tell it should be entirely harmless yeah, unless you use some kind of cursed tape that fuses the CPU to the socket or something lol. My first choice would be a tiny piece of kapton tape, but in absence of that I wouldn't feel uncomfortable using regular everyday tape either, as long as it's thin, electrically insulating, and doesn't stick like glue.
Do keep in mind the diagram I showed is from the perspective of looking down at the socket, not the CPU. But even if you cover the wrong pad I can't think of any way that could cause permanent damage. Just in case though, I can't be held responsible for whatever happens, but I would never wish harm on a Tiny, I love the things. I would test this on my own unit in a heartbeat, if I had one.
ok i have some kaptons tape and got it, i have to cover the pad that 'mirrors' the pin in your diagram, yes?

just curious, what would an actual 'good reason' be to apply a lane reversal, like what does that actually achieve
 

WifiCable

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Dec 18, 2023
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ok i have some kaptons tape and got it, i have to cover the pad that 'mirrors' the pin in your diagram, yes?

just curious, what would an actual 'good reason' be to apply a lane reversal, like what does that actually achieve
Yes, you would have to mirror the the diagram along one axis, depending on which way you turn the CPU over. I'm sure you can figure that out lol.

And for 'good' reasons to use lane reversal, there's a few of them but none apply here, especially not on this generation of Intel CPUs. Forgive me for the essay, but you asked lol:

The main reason for lane reversal is to make routing the PCIe lanes from the CPU to the slot easier if the slot happens to be in a position where the lanes are in reverse order. For example the Acer Veriton N series of mini PCs does this as the PCIe slot is placed on the other side of the CPU socket than usual:
1778962150697.png
On a usual ATX motherboard the PCIe slot to CPU socket wiring would be similar to this:
1778962231227.png
And while at first glance it looks fine with the slot on the other side, once you actually try routing it you see it ends up in reverse order:
1778962285436.png1778962296934.png1778962309074.png
(Images only for illustrative purposes, this is not really proper routing lol)

Solving this with some kind of messed up routing on the PCB would be a nightmare, so the CPU's PCIe controller has built in support to map the lanes in reverse, so you can connect lane 15 from the PCIe slot to lane 0 on the CPU, and lane 0 from the PCIe slot to lane 15 on the CPU (and the lanes in between follow).

Another reason to use lane reversal on the CPU that used to be relevant until Intel's 11th gen, was to get x4x4 bifurcation on either the upper or lower 8 lanes of the link. Those CPUs support splitting the x16 link into either 2 x8 links or 1 x8 link and 2 x4 links, but only in that order. This table from Intel's 8th generation CPU datasheet shows it:
1778963402491.png
So if you wanted to have x4x4 on lanes 0-7 from the CPU, you are forced to use lane reversal on the entire set of 16 lanes. This is what the bifurcation mod for the M920q/M920x/P330 does, since the riser slot there is connected to lanes 0-7.
j4cbo's PCIe x4 + 2xNVMe riser is wired with the slots from the CPU in reverse for that reason.

As you can see in the table, lane reversal and bifurcation is configured with 'CFG Signals'. These are pins on the CPU connected to resistor straps placed on the motherboard. (Resistor straps are simply little resistors that pull the relevant CFG pins on the CPU down to ground (0) or up to the IO voltage supply (1)). Lane reversal specifically is configured with pin CFG[2].


Now, in our case with the 12-14th gen tinies, the second reason is irrelevant because Intel removed x8x4x4 bifurcation from the generations using LGA1700, only leaving x16 and x8x8 support.
What Lenovo has done on these is pull both CFG[5] and CFG[2] down to ground (0), which sets the PCIe controller to x8x8 bifucation and lane reversal. The physical wiring on the official x16 riser card and motherboard connects the PCIe slot's lanes 0-7 to the CPU's lanes 8-15, which according to the table in Intel's 12th generation CPU datasheet maps it to PCIe010 lanes 7-0 with the CFG straps set as they are:
1778962692811.png
This effectively gives us a reversed x8 link on the PCIe slot.

Our goal now is to instead get a non-reversed link on lanes 8-15 on the CPU. Since the riser slot is connected to lanes 8-15, x8x8 bifurcation is required in order to get lane 0 of our PCIe link on the CPU's lane 8, so our only option is to leave CFG[5] pulled to ground and change CFG[2] to be pulled up instead. This gets our PCIe slot's lanes 0-7 mapped to PCIe011 lanes 0-7.
(We don't have to worry about what happens to the CPU's lanes 0-7, those aren't connected on these generations. As far as I know only Tiny7 (M90q Gen 2 & P350 Tiny) used all 16 lanes from the CPU, to get PCIe Gen 4 on the NVMe slots using x8x4x4).

Luckily we don't have to install a pullup resistor as the CPU has built in pullups which set the default state of all CFG pins to 1 if there is no strap connected.
Therefore all we need to do is sever the connection between the CFG[2] pin on the CPU and the resistor that pulls it down, which we can do by either removing the resistor or masking the pin.




Anyway that's why we can solve this with a tiny piece of tape, in theory at least, lol.
If you read all this, thanks. I have a lot to say about modern PC hardware design and I love teaching others about it <3
-Wifi
 
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WifiCable

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The most ridiculous part about this to me, is that Lenovo had the resistor set correctly on the Revision 0.5 (blue) prototype version of this motherboard (compared to the Revision 1.0 final one (green)):
1778966408754.png1778966412306.png

It makes me feel like they MUST have known. Why did they change it??
 
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besseddrest

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May 14, 2025
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Yes, you would have to mirror the the diagram along one axis, depending on which way you turn the CPU over. I'm sure you can figure that out lol.

And for 'good' reasons to use lane reversal, there's a few of them but none apply here, especially not on this generation of Intel CPUs. Forgive me for the essay, but you asked lol:

The main reason for lane reversal is to make routing the PCIe lanes from the CPU to the slot easier if the slot happens to be in a position where the lanes are in reverse order. For example the Acer Veriton N series of mini PCs does this as the PCIe slot is placed on the other side of the CPU socket than usual:
View attachment 48799
On a usual ATX motherboard the PCIe slot to CPU socket wiring would be similar to this:
View attachment 48800
And while at first glance it looks fine with the slot on the other side, once you actually try routing it you see it ends up in reverse order:
View attachment 48801View attachment 48802View attachment 48803
(Images only for illustrative purposes, this is not really proper routing lol)

Solving this with some kind of messed up routing on the PCB would be a nightmare, so the CPU's PCIe controller has built in support to map the lanes in reverse, so you can connect lane 15 from the PCIe slot to lane 0 on the CPU, and lane 0 from the PCIe slot to lane 15 on the CPU (and the lanes in between follow).

Another reason to use lane reversal on the CPU that used to be relevant until Intel's 11th gen, was to get x4x4 bifurcation on either the upper or lower 8 lanes of the link. Those CPUs support splitting the x16 link into either 2 x8 links or 1 x8 link and 2 x4 links, but only in that order. This table from Intel's 8th generation CPU datasheet shows it:
View attachment 48805
So if you wanted to have x4x4 on lanes 0-7 from the CPU, you are forced to use lane reversal on the entire set of 16 lanes. This is what the bifurcation mod for the M920q/M920x/P330 does, since the riser slot there is connected to lanes 0-7.
j4cbo's PCIe x4 + 2xNVMe riser is wired with the slots from the CPU in reverse for that reason.

As you can see in the table, lane reversal and bifurcation is configured with 'CFG Signals'. These are pins on the CPU connected to resistor straps placed on the motherboard. (Resistor straps are simply little resistors that pull the relevant CFG pins on the CPU down to ground (0) or up to the IO voltage supply (1)). Lane reversal specifically is configured with pin CFG[2].


Now, in our case with the 12-14th gen tinies, the second reason is irrelevant because Intel removed x8x4x4 bifurcation from the generations using LGA1700, only leaving x16 and x8x8 support.
What Lenovo has done on these is pull both CFG[5] and CFG[2] down to ground (0), which sets the PCIe controller to x8x8 bifucation and lane reversal. The physical wiring on the official x16 riser card and motherboard connects the PCIe slot's lanes 0-7 to the CPU's lanes 8-15, which according to the table in Intel's 12th generation CPU datasheet maps it to PCIe010 lanes 7-0 with the CFG straps set as they are:
View attachment 48804
This effectively gives us a reversed x8 link on the PCIe slot.

Our goal now is to instead get a non-reversed link on lanes 8-15 on the CPU. Since the riser slot is connected to lanes 8-15, x8x8 bifurcation is required in order to get lane 0 of our PCIe link on the CPU's lane 8, so our only option is to leave CFG[5] pulled to ground and change CFG[2] to be pulled up instead. This gets our PCIe slot's lanes 0-7 mapped to PCIe011 lanes 0-7.
(We don't have to worry about what happens to the CPU's lanes 0-7, those aren't connected on these generations. As far as I know only Tiny7 (M90q Gen 2 & P350 Tiny) used all 16 lanes from the CPU, to get PCIe Gen 4 on the NVMe slots using x8x4x4).

Luckily we don't have to install a pullup resistor as the CPU has built in pullups which set the default state of all CFG pins to 1 if there is no strap connected.
Therefore all we need to do is sever the connection between the CFG[2] pin on the CPU and the resistor that pulls it down, which we can do by either removing the resistor or masking the pin.




Anyway that's why we can solve this with a tiny piece of tape, in theory at least, lol.
If you read all this, thanks. I have a lot to say about modern PC hardware design and I love teaching others about it <3
-Wifi
okay so a lot of this is way over my head but what i'm getting is that its a way to accommodate standard connectors given the limited space - apologies as i'm a bit of a skimmer but i do appreciate the effort and plan to read it back closer but i'm just excited to test this out for ya and potentially upgrade my dGPU!

i'm on my work computer right now, trying this out.i didn't realize how small of a piece of tape i need lol

i'm trying to figure out an appropriate order of testing this as i want to be thorough, if i cover this pad up would should i still expect my WX 3200 to function (pcie x8)

i'm on a i5-13500T and basically yeah would like to make sure the following all work:
  1. WX-3200 pcie x8 // current
  2. RX 6400 pcie x4 // desired
  3. iGPU // should be unaffected
 

besseddrest

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May 14, 2025
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btw
1778998457627.png
1778998789450.png

Holy Crap.

So, it took forever to just cut a tiny piece of kapton tape small enough and even longer to just place it on the pad and ultimately there was a tiny corner of pad sneaking out - but i figured - i just need to prevent the pin from touching the pad, and i don't want to block other pads

First boot I tried w/ the previous card removed, so internal graphics, no issue

2nd boot i just went straight to riser + RX 6400, no issue

And for context, when i initially put this machine together and got my hands on the RX 6400, i've tried every single non invasive solution trying to get this to work but never any signal. I even just took a shot in the dark with the WX 3200 because I believe it's listed compatible on some other model spec sheet, maybe prior to the P3 - i figured, well maybe its cuz its a 'workstation' card.

Glad i didn't resell this 6400, was saving it for another build but i'm really happy that it seems to be working w/ no hiccups!

Happy to sync separately w WifiCable if there's any system level info you want me to look up, thank you thank you thank you.
 
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WifiCable

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Aw heck yeah, that's what I was hoping to see! Awesome.
To answer your earlier question, anything that worked before should continue to work with lane reversal disabled. It's more surprising to me how many things *did* work with it in the first place lol. Kind of makes it a cool platform to experiment with testing the capabilities of different card manufacturers' PCIe controllers, though limited to x8 and x16 cards.

From how you describe it it sounds like it was pretty difficult to get the tape cut to size and stuck down. Do you think there would be value in designing a custom riser that wires the lanes in reverse? Like, would you rather do this mod with the tape or buy/assemble a riser that solves it for you (and maybe has some extra features).

If it's not too much trouble, could you share a picture of your CPU with the tape applied to the pin? I'd like to have a good picture to add to my TinySecrets documentation for others to reference.
And hey, congrats on finally getting the setup you wanted working ^_^
Thanks for giving it a try!
 

besseddrest

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May 14, 2025
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Aw heck yeah, that's what I was hoping to see! Awesome.
To answer your earlier question, anything that worked before should continue to work with lane reversal disabled. It's more surprising to me how many things *did* work with it in the first place lol. Kind of makes it a cool platform to experiment with testing the capabilities of different card manufacturers' PCIe controllers, though limited to x8 and x16 cards.

From how you describe it it sounds like it was pretty difficult to get the tape cut to size and stuck down. Do you think there would be value in designing a custom riser that wires the lanes in reverse? Like, would you rather do this mod with the tape or buy/assemble a riser that solves it for you (and maybe has some extra features).

If it's not too much trouble, could you share a picture of your CPU with the tape applied to the pin? I'd like to have a good picture to add to my TinySecrets documentation for others to reference.
And hey, congrats on finally getting the setup you wanted working ^_^
Thanks for giving it a try!
shit i shoulda taken a picture prior to installing! i'll try to get you some photos

i mean, i guess you can say it was difficult; but it's more like i could see this being extremely frustrating for those who are a bit more clumsy. After you cut something so small even the force of your cutting tool can flick away the piece you were targeting, lol. Eventually i managed a technique with the pointy ends of some spudgers

That being said, I don't know that I go with the custom riser version if I didn't think I had the patience to accomplish this. I think if this mod unlocks a lot more add-on options, then I guess i've already done the hard part. i don't change my CPU enough. i suppose it depends on what "extra features" encompasses. But yeah it's a spare card I had laying around, there aren't very many other cards within my price range, and so cutting the tape is prob the approach i go with most of the time

Thanks again - i actually forked your repo and i can commit an image for you there, i was going to add a line here and there for m75q gen 2, maybe any notes i have re: P3, dGPUs

Once again, thank you very much!!!
 

Bacterium

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Oct 3, 2025
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@WifiCable

From how you describe it it sounds like it was pretty difficult to get the tape cut to size and stuck down. Do you think there would be value in designing a custom riser that wires the lanes in reverse? Like, would you rather do this mod with the tape or buy/assemble a riser that solves it for you (and maybe has some extra features).
I will probably do the tape mod at least initially. But I'd be curious to know what
extra features
you have in mind, as I'd been looking out for custom risers for the P360.
 
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besseddrest

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@WifiCable or anyone else, related question:

My system has both a iGPU and dGPU, and I use a single monitor setup. I'd like to understand if its possible to take advantage of a hybrid graphics setup somehow - i just can't wrap my head around it because to me in order for me to 'enable' one or the other, it's output needs to be plugged in - so that would put my iGPU & dGPU on two separate inputs on my monitor, let's say DP1 = dGPU, and DP2 = iGPU

w my previous dGPU i had both plugged in the DP1 and DP2 but i wasn't really sure if anything was happening; I primarily stay on DP1.

I'm on Arch Linux, Lenovo p3 Tiny gen 1. One thought I have is my system might already do this dynamically, but I'm unsure if in that case I need both plugged in to my monitor

Open to any suggestions of how to take advantage of both GPUs, or if I really gain anything from doing so, or if it's even possible at all given my single monitor setup. Thanks!
 

jlist

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Jan 22, 2024
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@WifiCable or anyone else, related question:

My system has both a iGPU and dGPU, and I use a single monitor setup. I'd like to understand if its possible to take advantage of a hybrid graphics setup somehow - i just can't wrap my head around it because to me in order for me to 'enable' one or the other, it's output needs to be plugged in - so that would put my iGPU & dGPU on two separate inputs on my monitor, let's say DP1 = dGPU, and DP2 = iGPU

w my previous dGPU i had both plugged in the DP1 and DP2 but i wasn't really sure if anything was happening; I primarily stay on DP1.

I'm on Arch Linux, Lenovo p3 Tiny gen 1. One thought I have is my system might already do this dynamically, but I'm unsure if in that case I need both plugged in to my monitor

Open to any suggestions of how to take advantage of both GPUs, or if I really gain anything from doing so, or if it's even possible at all given my single monitor setup. Thanks!

I did this on Windows 11, but I assume Linux can also be configured to have similar behavior.

I have a P330 with a Quadro P1000, and at that time I didn't have a mDP cable lying around so I connected the HDMI cable from the monitor to the P330 mobo's HDMI port. Windows uses the P1000 to render the games and benchmarks, and then the screen output is sent to the iGPU which is further sent to the monitor for displaying. So despite the dGPU not being connected to the monitor, it's still doing work.

In Windows, programs are automatically assigned to either be low-powered (uses the iGPU) or high-performance (uses the dGPU), but you can specifically change it to the other type if you prefer. So if you have a browser and a game opened, the iGPU can work on the video decoding for Youtube while the dGPU focuses on the game.

By the way, this is similar to how laptops with a dGPU work. Even if it has a dGPU the laptop screen is connected to the iGPU so it still has to go through it (unless the laptop has a MUX switch, which lets you disable the iGPU and have the dGPU connect directly to the monitor for improved performance and battery life).

If you're asking about how to have both the dGPU and iGPU work together in a single app, then I think that program has to be specifically programmed for it so it's on a case-by-case basis.
 
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jja2000

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Hello everyone, I'm looking for some volunteers who might want to test a theory on a Tiny8+ machine.
The boardview for the M90q Gen 3/P360 Tiny (NM-D581) recently became available, and after me and some others looked through it for a while we found out the possible cause of the issue where PCIe x4 and x1 cards don't work in the x16/x8 riser on these machines: Tiny8 riser pinout · Issue #1 · qq8322302/P3Tiny-PCIE-Card
Also discussing it here: https://forums.servethehome.com/ind...-2-connector-and-much-more.52689/#post-503708

It turns out that Lenovo has activated lane reversal on the CPU's PCIe lanes for no good reason, which is causing the x8 link on the riser slot to be set up in reverse lane order. For most x8+ cards this seems to work fine as they have their own lane reversal support built in, but for example, if you install a x4 card this causes it to be connected to lanes 7-4 of the x8 link instead of 0-3, which doesn't work.

There are a few ways to address this:
- Remove the pulldown resistor on the CPU's CFG2 line from the motherboard.
- Mask the CFG2 pad on the CPU
- Build a riser that routes the PCIe lanes in reverse

I feel a bit iffy about designing a riser that connects the lanes in reverse, because:
1: There's at least one example of a x4 card working in the x16 riser: youtube.com/watch?v=W4wt1ioIkY4
So it's possible not all machines are affected by this and would instead manifest this issue with a riser wired in reverse.
2: Future machines using the same riser slot might not have the link configured in reverse

So far I've looked at available board images from Lenovo's parts catalog and all pictures I could find of M90q Gen 3, Gen 4 and Gen 5, as well as the P360 Tiny, P3 Tiny and Neo Ultra's boards have the strap resistors set to activate lane reversal, but not all FRUs have images available, so I can't be sure that definitely every board with the Tiny8 riser slot uses lane reversal. This is especially the case for the latest M90q Gen 6, P3 Tiny Gen 2 and Neo Ultra Gen 2 models because on that generation Intel switched to using firmware straps for setting lane reversal, so there's no way to tell visually.

In conclusion, since I don't have a Tiny8 riser slot machine to test with, I'm asking the community for 2 things.
If you own an M90q Gen 3, Gen 4, Gen5, a P360 Tiny a P3 Tiny (Gen 1) or a Neo Ultra (Gen 1),

1: Would you be willing to test if either removing the marked resistor here (invasive): View attachment 48756
or masking this pad on the CPU (socket perspective in the picture, less invasive): View attachment 48757
fixes compatibility with x4 and smaller cards when using the x16 riser?

2: If you don't wanna test an unverified mod on your machine, it would still be very helpful if you could take a picture of the CFG resistor area next to the CPU socket (the area in the resistor removal picture above), I'm hoping to collect pictures from as many different machines as possible to find if there are any outliers which might have them set differently than I've seen so far.


This information would both help people who want to use x4 and x1 cards in the original x16/x8 riser, and would also be very useful for me and other custom riser developers to choose how to proceed.
Thanks a lot in advance!
Hi! I've rage posted a couple of times in this thread about my Intel Arc Pro B50 not working well in my M90q Gen 5 (with riser 5C50W00933):
1. If ASPM is enabled it never works, there is a suspicious error in dmesg:
pcieport 0000:01:00.0: Unable to change power state from D3cold to D0, device inaccessible on a PCIe device "PCI bridge: Intel Corporation Device e2ff (rev 01)". It has a x8 PCIe link according to Linux so it _sounds_ like the riser and B50 (EDIT: confirmed, doesn't show up when I remove the riser and B50).
2. If ASPM is disabled it sometimes will work.
- When it does not: There is no display, plugging in into the iGPU shows that the nvme drives are unavailable throwing the same "device inaccessible" error as above, but thrown out by the nvme kernel driver.
- When it does: It can boot and it works fine (until the driver crashes, but I'm not sure if that has to do with the PCIe device setup this board has).

Now my predicament. Your solution sounds like one that would work on my device. Although the B50 is an x8 device, I wouldn't be surprised the ASPM options it supports may be putting it in a lower power state that limits lanes. Therefore falling in the "using a lower lane device in an x8/x16 slot". Turning off ASPM, however, may be inducing other issues on several of the other devices on this board that impede usage, not to mention that display doesn't even come up on the B50.

If I try this out, will higher bandwidth still be available for the B50 to use? I haven't tried a different card in this yet, but your explanation gives me some hopium to huff.

ANOTHER EDIT: Worth mentioning I tried using a x4 card in the riser before and it didn't work. I think the board may have the same lane reversing setup.
 
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besseddrest

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May 14, 2025
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I did this on Windows 11, but I assume Linux can also be configured to have similar behavior.

I have a P330 with a Quadro P1000, and at that time I didn't have a mDP cable lying around so I connected the HDMI cable from the monitor to the P330 mobo's HDMI port. Windows uses the P1000 to render the games and benchmarks, and then the screen output is sent to the iGPU which is further sent to the monitor for displaying. So despite the dGPU not being connected to the monitor, it's still doing work.

In Windows, programs are automatically assigned to either be low-powered (uses the iGPU) or high-performance (uses the dGPU), but you can specifically change it to the other type if you prefer. So if you have a browser and a game opened, the iGPU can work on the video decoding for Youtube while the dGPU focuses on the game.

By the way, this is similar to how laptops with a dGPU work. Even if it has a dGPU the laptop screen is connected to the iGPU so it still has to go through it (unless the laptop has a MUX switch, which lets you disable the iGPU and have the dGPU connect directly to the monitor for improved performance and battery life).

If you're asking about how to have both the dGPU and iGPU work together in a single app, then I think that program has to be specifically programmed for it so it's on a case-by-case basis.
yeah looks like i have options like 'switcheroo-control' for a GUI focused option and PRIME to be configuration based - both to provide GPU assignment at an app level