It should work. You'll need to DL bios from Lenovo and extract the bios file from the exe. There are a bunch of vids on YT explaining the process to recover from a bad bios.
Lenovo M700/M900 BIOS mod to Coffee Lake CPUs
- Thread starter mobilenvidia
- Start date
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Thank you for your answer.
I try it but now the power led blink. And the fan just start when led is on and is stop with the power led
I don’t know what is the problem.
I try it but now the power led blink. And the fan just start when led is on and is stop with the power led
I don’t know what is the problem.
Is this explained anywhere? I can't figure it out.
I tried without doing it. But not able to get the i5-7500T to post in the M700.
EDIT: Maybe figured it out.
EDIT2: Got it working, I think. However I cannot get it to detect any SATA drive. And it is missing the UUID, SN, etc.
EDIT3: Not really sure what I'm doing wrong. I've tried the process a few times. The MAC is getting copied over from original. But UUID, SN are not. And I've never been able to get SATA working.
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On my system (same board), SATA drives don't show in the BIOS but they are are visible to the OS, and are bootable.
Went on to try coreboot. Like a week and a 100 flashes later. Making progress.
SeaBIOS payload is working perfectly. Booted up to live Ubuntu and everything seems to be working. However, SeaBIOS is legacy only.
I simply cannot get edk2 to work. It seems to POST as my CAPS / NUM lock turn on the LEDs on the keyboard. The display turns on but its just a blank screen.
EDIT: Making progress. Have finally got a basic edk2 to work.
EDIT2: FINALLY!
What my issue, was changing Devices -> Display -> Framebuffer mode to Linear "high resolution" frame buffer.
Kaby Lake is working perfectly fine as well.
SeaBIOS payload is working perfectly. Booted up to live Ubuntu and everything seems to be working. However, SeaBIOS is legacy only.
I simply cannot get edk2 to work. It seems to POST as my CAPS / NUM lock turn on the LEDs on the keyboard. The display turns on but its just a blank screen.
EDIT: Making progress. Have finally got a basic edk2 to work.
EDIT2: FINALLY!
What my issue, was changing Devices -> Display -> Framebuffer mode to Linear "high resolution" frame buffer.
Kaby Lake is working perfectly fine as well.
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My guide to installing Coreboot on the M700 / M900. I haven't tried Coffee Lake yet, but Kaby Lake works fine. I will be buying one of the QJT1 engineering samples shortly for it. Secure boot works as does Windows 11 installs. Although I won't be using Windows, I am currently testing. I can't confirm if the Windows keys tied to the system work, as my M700s never had them to begin with. But the serial number & UUID should technically be preserved. I could not get coreboot to compile w/ CachyOS so I gave up and used Ubuntu.
Install software and dependencies. If i missed any, it should list them when you try to run a task. Then just install them.
Backup of your existing bios / rom
You should see an output of
Creating backup
Verify backup is the same as the bios chip
Extracting your ROM to pull descriptor, ME, GBE
It will create some files along the lines of flashregion_0_descriptor.bin, flashregion_1_me.bin, flashregion_2_gbe.bin. I can't remember the exact file names. But rename and move them
Setting up Coreboot
Security, Console, System tables don't need to be touched
Debugging and Boot Logo Configuration do not need to be touched.
At bottom of screen, click Save.
Creating and flashing
And done. Just disconnect the flasher, plug in power to M700. Should hopefully boot up after.
Install software and dependencies. If i missed any, it should list them when you try to run a task. Then just install them.
Code:
sudo apt-get install -y bison build-essential curl flex git gnat libncurses-dev libssl-dev zlib1g-dev pkgconf flashrom coreboot-utils
git clone https://review.coreboot.org/coreboot
cd coreboot
make help_toolchain
make -C payloads/coreinfo olddefconfig
make -C payloads/coreinfosudo flashrom -p ch341a_spi You should see an output of
Code:
flashrom unknown on Linux 7.0.0-28-generic (x86_64)
flashrom is free software, get the source code at https://flashrom.org
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
Found Winbond flash chip "W25Q128.V" (16384 kB, SPI) on ch341a_spi. sudo flashrom -p ch341a_spi -r backup.bin Verify backup is the same as the bios chip
sudo flashrom -p ch341a_spi -v backup.bin Extracting your ROM to pull descriptor, ME, GBE
cd util/ifdtool
make ./ifdtool -x ~/coreboot/backup.binIt will create some files along the lines of flashregion_0_descriptor.bin, flashregion_1_me.bin, flashregion_2_gbe.bin. I can't remember the exact file names. But rename and move them
Code:
mv flashregion_0_descriptor.bin ~/coreboot/descriptor.bin
mv flashregion_1_me.bin ~/coreboot/me.bin
mv flashregion_2_gbe.bin ~/coreboot/gbe.binSetting up Coreboot
cd ~/coreboot
make menuconfig
Code:
│ ┌───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐ │
│ │ () Local version string │ │
│ │ Compiler to use (GCC) ---> │ │
│ │ [ ] Allow building with any toolchain │ │
│ │ [] Use ccache to speed up (re)compilation │ │
│ │ [ ] Use link time optimization (LTO) (experimental) │ │
│ │ [ ] Test platform with include-what-you-use │ │
│ │ [ ] Generate flashmap descriptor parser using flex and bison │ │
│ │ [ ] Generate parsers for bincfg, sconfig and kconfig locally │ │
│ │ Option backend to use (None) ---> │ │
│ │ Ramstage compression (Compress ramstage with LZMA) ---> │ │
│ │ [*] Build a separate romstage │ │
│ │ [*] Include the coreboot .config file into the ROM image │ │
│ │ [*] Create a table of timestamps collected during boot │ │
│ │ [ ] Print the timestamp values on the console │ │
│ │ [*] Allow use of binary-only repository │ │
│ │ [ ] Allow AMD blobs repository (with license agreement) │ │
│ │ [ ] Allow QC blobs repository (selecting this agrees to the license!) │ │
│ │ [ ] Code coverage support │ │
│ │ [ ] Undefined behavior sanitizer support │ │
│ │ [ ] Address sanitizer support │ │
│ │ Stage Cache for ACPI S3 resume (TSEG) ---> │ │
│ │ [ ] Update existing coreboot.rom image │ │
│ │ [ ] Add a bootsplash image │ │
│ │ Software Bill Of Materials (SBOM) ---> │ │
│ │ │ │
Code:
│ ┌───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐ │
│ │ *** Important: Run 'make distclean' before switching boards *** │ │
│ │ Mainboard vendor (Lenovo) ---> │ │
│ │ Mainboard model (ThinkCentre M700 / M900 Tiny) ---> │ │
│ │ (ThinkCentre M700 / M900 Tiny) Mainboard part number │ │
│ │ (LENOVO) Mainboard vendor name │ │
│ │ ROM chip size (16384 KB (16 MB)) ---> │ │
│ │ System Power State after Failure (S0 Full On) ---> │ │
│ │ () fmap description file in fmd format │ │
│ │ (0x800000) Size of coreboot owned area in ROM │ │
Code:
│ ┌───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐ │
│ │ *** SoC *** │ │
│ │ [ ] Enable SATA test mode │ │
│ │ [*] Board can contain Skylake CPU │ │
│ │ [*] Board can contain Kaby Lake CPU │ │
│ │ [*] Board can contain Coffee Lake CPU │ │
│ │ *** Intel SoC Common Code for IP blocks *** │ │
│ │ Application Processors (AP) Feature Programming Configuration to use (Allow FSP running CPU f│ │
│ │ [ ] Perform MP Initialization by FSP │ │
│ │ [*] Enable Hyper-Threading │ │
│ │ [ ] Intel Key Locker │ │
│ │ PRMRR size (0 MiB) ---> │ │
│ │ [ ] Disable HECI1 at the end of boot │ │
│ │ [ ] CSE send EOP early │ │
│ │ [*] Disable write status SPI opcode │ │
│ │ [ ] Disable Integrated GFX Controller (0:2:0) │ │
│ │ [*] Enable ACPI PM timer │ │
│ │ [ ] Enable Software Guard Extensions (SGX) if available │ │
│ │ [ ] Enable TCO SMI │ │
│ │ [*] Use Legacy 8254 Timer │ │
│ │ *** Intel SoC Common Code for features *** │ │
│ │ *** Intel SoC Common PCH Code *** │ │
│ │ *** Intel SoC Common coreboot stages and non-IP blocks *** │ │
│ │ (0) Debug Consent for Intel SoC │ │
│ │ [*] Enable PAVP (Protected Audio-Video Path) support │ │
│ │ [ ] Enable MMA (Memory Margin Analysis) support for Intel Core │ │
│ │ [ ] Enable SOC debug interface │ │
│ │ *** CPU *** │ │
│ │ [*] Enable VMX for virtualization │ │
│ │ [*] Set IA32_FEATURE_CONTROL lock bit │ │
│ │ [*] Lock the AES-NI enablement state │ │
│ │ APIC operation mode (Set XAPIC mode) ---> │ │
│ │ Include CPU microcode in CBFS (Generate from tree) ---> │ │
│ │ *** Northbridge *** │ │
│ │ *** Southbridge *** │ │
│ │ [ ] Validate Intel firmware descriptor │ │
│ │ *** Super I/O *** │ │
│ │ *** Embedded Controllers *** │ │
│ │ *** Intel Firmware *** │ │
│ │ [*] Add Intel descriptor.bin file │ │
│ │ (descriptor.bin) Path and filename of the descriptor.bin file │ │
│ │ [*] Add Intel ME/TXE firmware │ │
│ │ [ ] Stitch individual ME/CSE components │ │
│ │ (me.bin) Path to management engine firmware │ │
│ │ [ ] Verify the integrity of the supplied ME/TXE firmware │ │
│ │ [ ] Allows HOST/CPU read access to ME region │ │
│ │ [ ] Strip down the Intel ME/TXE firmware │ │
│ │ [*] Add gigabit ethernet configuration │ │
│ │ (gbe.bin) Path to gigabit ethernet configuration │ │
│ │ Protect flash regions (Unlock flash regions) ---> │ │
│ │ Bootblock behaviour (Always load fallback) ---> │ │
│ │ [ ] Dump part of SMBIOS type17 dimm information │ │
│ │ │ │
Code:
│ ┌───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐ │
│ │ Graphics initialization (Use libgfxinit) ---> │ │
│ │ Early (romstage) graphics initialization (None) ---> │ │
│ │ [*] Use onboard VGA as primary video device │ │
│ │ Display ---> │ │
│ │ [*] Allow coreboot to set optional PCI bus master bits │ │
│ │ -*- PCI bridges │ │
│ │ [*] Any devices │ │
│ │ -*- Enable PCIe Common Clock │ │
│ │ [*] Enable PCIe ASPM │ │
│ │ [*] Enable PCIe Clock Power Management │ │
│ │ [*] Enable PCIe ASPM L1 SubState │ │
│ │ [ ] Support PCIe Resizable BARs │ │
│ │ [ ] Enable Clear PCIe Lane Error Status │ │
│ │ [ ] Enable PCIe Hotplug Support │ │
│ │ [ ] Early PCI bridge │ │
│ │ (0x0000) Override PCI Subsystem Vendor ID │ │
│ │ (0x0000) Override PCI Subsystem Device ID │ │
│ │ [ ] Add a VGA BIOS image │ │
│ │ [*] Add a Video BIOS Table (VBT) binary to CBFS │ │
│ │ (src/mainboard/$(MAINBOARDDIR)/data.vbt) VBT binary path and filename │ │
│ │ [ ] Enable I2C controller emulation in software │ │
│ │ (500000) I2C transfer timeout in microseconds │ │
│ │ [*] Allocate resources from top down │ │
│ │ [ ] Extend resource window for PCIe devices above 4G │ │
Code:
│ ┌───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐ │
│ │ -*- Include EFI variable store driver │ │
│ │ [ ] Expose firmware version in a EFI-friendly form │ │
│ │ [ ] Support for flash based event log │ │
│ │ [ ] HWID from CBFS for SMBIOS product name │ │
│ │ -*- Enable protection on MRC settings │ │
│ │ -*- Support generating a CFR list of options │ │
│ │ [*] Support for flash based, SMM mediated data store │ │
│ │ (0x80000) size of the SMMSTORE FMAP region │ │
│ │ [ ] Disable Fast Read command │ │
│ │ [ ] Generate ACPI code to implement TPM physical presence interface │ │
│ │ -*- Serial port on SuperIO │ │
│ │ [ ] Oxford OXPCIe952 │ │
│ │ [ ] Support for Vital Product Data tables │ │
│ │ [ ] qemu fw_cfg │ │
│ │ [*] Serial number in CBFS │ │
│ │ [*] System UUID in CBFS │ │
│ │ [ ] Genesys Logic GL9750 │ │
│ │ [ ] Genesys Logic GL9755 │ │
│ │ [ ] Genesys Logic GL9763E │ │
│ │ [ ] Enable AMP MAX98396 │ │
│ │ [*] Use binaries of the Intel FSP repository on GitHub │ │
│ │ (fsps.bin) Name of FSP-S in CBFS │ │
│ │ (fspm.bin) Name of FSP-M in CBFS │ │
│ │ [ ] Display FSP Timestamps │ │
│ │ [ ] Use Debug FSP for Build │ │
│ │ VBT Compression algorithm (Compress VBT with LZMA algorithm) ---> │ │
│ │ [*] Enable undervolting via OC mailbox │ │
│ │ [ ] NXP UWB SR1xx driver │ │
│ │ [ ] PS/2 keyboard init │ │
│ │ [*] Use legacy-BIOS alt-century byte in CMOS │ │
│ │ [ ] Silicon Image SIL3114 │ │
│ │ [*] Support Intel PCI-e WiFi adapters │ │
│ │ [ ] Support MediaTek PCI-e WiFi adapters │ │Change Payload to add to edk2 payload. And make sure Tianocore's EDK 2 payload is MrChromebox' edk2 fork
Code:
│ ┌───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐ │
│ │ [ ] Don't add a payload │ │
│ │ Payload to add (edk2 payload) ---> │ │
│ │ (build/UEFIPAYLOAD.fd) edk2 binary │ │
│ │ EDK II build type (Build UefiPayloadPkg) ---> │ │
│ │ Tianocore's EDK II payload (MrChromebox' edk2 fork) ---> │ │
│ │ (https://github.com/mrchromebox/edk2) URL to git repository for edk2 │ │
│ │ (origin/uefipayload_2605) Insert a commit's SHA-1 or a branch name │ │
│ │ [ ] Use edk2-platforms repository │ │
│ │ edk2 build (Generate edk2 release build) ---> │ │
│ │ (Documentation/coreboot_logo.bmp) edk2 Bootsplash path and filename │ │
│ │ [*] Use Escape key for Boot Manager │ │
│ │ (2) Set the timeout for boot menu prompt │ │
│ │ [ ] Enable edk2 logging to CBMEM │ │
│ │ [ ] Center logo 38.2% from the top of screen │ │
│ │ [*] Use the full screen for the edk2 frontpage │ │
│ │ [*] Include EFI Shell │ │
│ │ [*] Prioritize internal boot devices │ │
│ │ [ ] Load and Execute OpROMs on PCIe devices │ │
│ │ [*] Support PS/2 Keyboards │ │
│ │ (10) Timeout in ms for initializing SD and eMMC devices │ │
│ │ [ ] Enable serial console │ │
│ │ [*] Enable UEFI Secure Boot support │ │
│ │ [*] Use the LVGL graphical setup renderer │ │
│ │ [ ] Disable TPM support in edk2 │ │
│ │ [ ] Use LAPIC timer instead of HPET │ │
│ │ () edk2 additional custom build parameters │ │
│ │ [ ] Include iPXE in edk2 payload │ │
│ │ [ ] Add a PXE ROM │ │
│ │ Payload compression algorithm (Use LZMA compression for payloads) ---> │ │
│ │ [*] Use LZMA compression for secondary payloads │ │
│ │ Secondary Payloads ---> │ │At bottom of screen, click Save.
Creating and flashing
make This will take a while. Could be 30+ minutes. If it fails. Hopefully it is just a missing dependancy, that you can install.sudo flashrom -p ch341a_spi -w build/coreboot.rom This will take about 5 minutes.And done. Just disconnect the flasher, plug in power to M700. Should hopefully boot up after.
I tried to install it twice. Both different versions of Windows. I've never encountered this ever before. And I can't find people with similar issues via google. After it updates and creates your profile. It errors out "The Remote Desktop Configiration service failed the sign-in. You hit ok. It reboots. And you create a new profile. After this you can login. And even login to the original profile you created. Windows Update seems to work fine. After installing Intel chipset drivers, there was one holdout that a driver wasn't found "PCI Data Acquisition and Signal Processing Controller". No idea what this is.
After flashing to CoreBoot, are you able to do subsequent flashing from within the OS or do you still need to use the CH341a?
I think technically you could, as long as you are using linux. You can read and write from the internal bios chip w/ flashrom. And there won't be a lock in place no longer. I guess you don't need to permanently run it. Just run a light linux on a thumb drive when / if you need to update.
Got 2nd M700 flashed. This time replacing FW on my M700 running OPNSense. I don't use Wifi, but the wifi slot works w/ a GBE Intel adapter.
Now just to figure out how to undervolt a machine. I want to use the QJT1 but need to lower PL1 and PL2 so I can do it safely.
Thanks to everyone who contributed to this thread. It’s an absolute goldmine of information!
I managed to bring my M700 back to life by flashing the BIOS shared by one of the members in the previous pages using a CH341A programmer.
Since I had an i5-7600T and a CH341A on hand, I decided to try the BIOS mod myself. By following the information in this thread, I successfully merged the original M700 BIOS with the M710q BIOS, then used CoffeeTime to patch the necessary options, as well as the script to unlock the hidden BIOS settings.
I flashed the modified BIOS, ran several tests, and everything works perfectly with the i5-7600T.
The BIOS initially showed invalid serial numbers and model information, but I restore them using Lenovo’s amidedos.exe utility.
The only issue, as several people have already mentioned, is that SATA HDDs and SSDs are not detected in the BIOS. However, they are still bootable and are correctly detected by the operating system, so this isn’t a problem for me.
I also no longer have the Windows product key stored in the BIOS, but that’s not an issue for my use case since this machine runs Linux. It may be possible to restore it using amidedos, but I haven’t tried.
Thanks again to everyone who shared their knowledge and experience. It allowed me not only to recover my M700 but also to discover the fascinating world of BIOS modding.
I managed to bring my M700 back to life by flashing the BIOS shared by one of the members in the previous pages using a CH341A programmer.
Since I had an i5-7600T and a CH341A on hand, I decided to try the BIOS mod myself. By following the information in this thread, I successfully merged the original M700 BIOS with the M710q BIOS, then used CoffeeTime to patch the necessary options, as well as the script to unlock the hidden BIOS settings.
I flashed the modified BIOS, ran several tests, and everything works perfectly with the i5-7600T.
The BIOS initially showed invalid serial numbers and model information, but I restore them using Lenovo’s amidedos.exe utility.
The only issue, as several people have already mentioned, is that SATA HDDs and SSDs are not detected in the BIOS. However, they are still bootable and are correctly detected by the operating system, so this isn’t a problem for me.
I also no longer have the Windows product key stored in the BIOS, but that’s not an issue for my use case since this machine runs Linux. It may be possible to restore it using amidedos, but I haven’t tried.
Thanks again to everyone who shared their knowledge and experience. It allowed me not only to recover my M700 but also to discover the fascinating world of BIOS modding.