Intel Cascade Lake-AP Is This 4P Cascade Lake Xeon in 2P

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AdrianB

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Mar 3, 2017
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[QUOTE=" Getting to a 1.35x performance factor would imply using 12x DDR4-2400 (Cascade Lake-AP) versus 8x DDR4-2666 (Naples.) This would be truly strange to see memory speeds go down but the math is hard to work out otherwise if one has 50% more memory channels. "[/QUOTE]


I do not see anything strange in this.

If this speed estimation is true, then using 12 channels of DDR4 @ 2666 increases the power consumption over the thermal limit of the single socket used for Cascade Lake-AP.

To limit the TDP to a reasonable value less than twice that of Xeon 8160, e.g. to 250 W, they probably had to downclock a little the memory controllers.
 

Evan

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Jan 6, 2016
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It’s only a matter of time before all software vendors go back to per core license I guess...
Then having for a lot of commercial applications a lot of slower cores making not that much sense, you want then a better balance of cores vs core speed. Of course for HPC and other workloads it will continue to make sense.
 

markarr

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Oct 31, 2013
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Both Oracle and MS use per core licenses, in some of their products ie: Oracle DB and Windows Server. Oracle is adding Java which will be either "named user" or per core. It will be interesting to see when vmware will follow the path.
 

Evan

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Jan 6, 2016
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Not to want to get off track but that oracle license cost for Java is just silly, I can’t think users will take to it and say oh what a great idea let’s use more java... direction where I work is to use less of course.
I guess oracle are hoping it’s just too hard for people not to use it.
 

cactus

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Jan 25, 2011
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Is the per socket market large enough to support this thing? Seems like marketing just wants to "beat" AMD.
Routing a 2x3647 pin socket will be interesting. The Epyc 2S boards with 32 DIMMs already take up most of the width of a normal board. I'd assume Intel uses buffered memory again, but that means Intel planned this and have a successor to the C104 that can support DDR4. The C104 could do dual DDR3 and connected to the chip with a 2667MT interface. So dual DDR4 2400, 4800MT connection to the CPU? (seems right with the throughput) Then they only have to have 112*6 pins for dodeca-channel DDR4-2400 and can do memory riser boards so the whole thing fits in a chassis with PCIe.
 

Patrick

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Dec 21, 2010
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@cactus the bigger question now is how much, if any, changes are being made for this in the silicon or is it mostly just a packaging exercise.
 
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