GIGABYTE MZ31-AR0 REV 1.1 with Epyc Rome / Milan

[RolloZ170]

plan was to have a board with Rome compatible VR version to extract the data with PowerIRCenter+USB005,
and program a Naples only board.
now i have a Naples only board without a VRM header to program, i found two resistors to contact SDA/SCL of IR35201.

 

[RolloZ170]

i created a new design in PowIRCenter with IR35201 load standard AMD 6+2
save config. file gives this

Spoiler: code list

17 00 00
24 90 FF
25 22 FF
26 10 FF
27 2E FF
28 C8 FF
29 46 FF
2A 00 FF
2B 00 FF
2C 00 FF
2D 00 FF
2E 00 FF
2F 00 FF
30 00 FF
31 00 FF
32 00 FF
33 00 FF
34 00 FF
35 E4 FF
36 E8 FF
37 34 FF
38 28 FF
39 FF FF
3A 00 FF
3B 5C FF
3C 58 FF
3D 00 FF
3E 00 FF
3F 5D FF
40 A2 FF
41 69 FF
42 69 FF
43 A0 FF
44 21 FF
45 29 FF
46 8A FF
47 34 FF
48 90 FF
49 D4 FF
4A D4 FF
4B 90 FF
4C 4C FF
4D 08 FF
4E 71 FF
4F 00 FF
50 E0 FF
51 AA FF
52 A0 FF
53 90 FF
54 A0 FF
55 90 FF
56 C2 FF
57 84 FF
58 50 FF
59 00 FF
5A 00 FF
5B F9 FF
5C 54 FF
5D 14 FF
5E 88 FF
5F 00 FF
60 80 FF
61 00 FF
62 40 FF
63 00 00
64 00 00
65 00 FF
66 AA FF
67 00 FF
68 EE FF
69 AA FF
6A 08 FF
6B 01 FF
6C 01 FF
6D 44 FF
6E 11 FF
6F 22 FF
70 83 FF
71 50 FF
72 51 FF
73 FF FF
74 BB FF
75 7B FF
76 83 FF
77 C2 FF
78 61 FF
79 39 FF
7A 00 FF
7B 88 FF
7C 10 FF
7D 00 FF
7E 00 FF
7F 00 FF
80 00 FF
81 07 FF
82 00 FF
83 52 FF
84 49 FF
85 00 FF
86 00 FF
87 50 FF
88 01 FF
89 00 FF
8A 00 FF
8B 00 FF
8C 00 FF
8D 00 FF
8E 00 FF
8F 00 FF
90 00 FF
91 00 FF
92 00 FF
93 00 FF
94 00 FF
95 00 FF
96 00 FF
97 00 00
98 D4 FF
99 FC FF
9A 00 FF
9B 00 FF
9C 00 FF
9D 00 FF
9E FF FF
9F FF FF
A0 20 FB
A1 06 FF
A2 23 FF
A3 F0 FF
A4 06 FF
A5 16 FF
C2 71 00

the BIOS VR file 8144 is binary, i have converted to Hex string.

Spoiler: code list

24 20 FF
25 22 FF
26 10 FF
27 22 FF
28 FF FF
29 F0 FF
2A 00 FF
2B 00 FF
2C 66 FF
2D 66 FF
2E 60 FF
2F 30 FF
30 00 FF
31 00 FF
32 00 FF
33 00 FF
34 00 FF
35 E8 FF
36 EE FF
37 0C FF
38 14 FF
39 FF FF
3A 00 FF
3B 5E FF
3C 1A FF
3D 10 FF
3E 10 FF
3F 23 FF
40 A0 FF
41 2D FF
42 48 FF
43 9D FF
44 23 FF
45 30 FF
46 34 FF
47 19 FF
48 90 FF
49 DA FF
4A D8 FF
4B 48 FF
4C 48 FF
4D 08 FF
4E 71 FF
4F 00 FF
50 E0 FF
51 AA FF
52 A0 FF
53 88 FF
54 A0 FF
55 88 FF
56 C1 FF
57 C4 FF
58 50 FF
59 02 FF
5A 00 FF
5B F9 FF
5C 5E FF
5D 1E FF
5E 88 FF
5F 00 FF
60 00 FF
61 80 FF
62 80 FF
65 00 FF
66 AA FF
67 00 FF
68 0C FF
69 FC FF
6A 20 FF
6B 01 FF
6C 59 FF
6D 00 FF
6E 11 FF
6F 22 FF
70 03 FF
71 74 FF
72 00 FF
73 FF FF
74 9D FF
75 6B FF
76 84 FF
77 13 FF
78 61 FF
79 39 FF
7A 64 FF
7B 88 FF
7C 00 FF
7D 00 FF
7E 00 FF
7F 00 FF
80 00 FF
81 07 FF
82 00 FF
83 52 FF
84 49 FF
85 00 FF
86 00 FF
87 00 FF
88 01 FF
89 04 FF
8A 81 FF
8B 44 FF
8C 00 FF
8D 00 FF
8E 00 FF
8F 00 FF
90 00 FF
91 00 FF
92 00 FF
93 00 FF
94 00 FF
95 00 FF
96 00 FF
98 D4 FF
99 FC FF
9A 00 FF
9B 00 FF
9C 00 FF
9D 00 FF
9E FB FF
9F FB FF
A0 20 FB
A1 26 FF
A2 23 FF
A3 F0 FF
A4 06 FF
A5 16 FF

 

[RolloZ170]

MZ31-AR0 rev.1.1
used VR controllers for cpu are:
IR35201 0x24 Loop1 0x78 icc_max 240A (cores)
IR35204 0x25 Loop1 0x7A icc_max 80A (SoC)



does anyone have a picture of a MZ31-AR0 Ver. 2.x or 3.x ?

 

[RolloZ170]

bad news:
have seen register 0x28 goes from F0 (240A) to FF (255A) icc_max.
i can only access the VRM with powered CPU.
so i power the board, press pwr_btn and changed registers to the 8144 file given from the BIOS,
but i can't get ROme to work.
unfortunaly the written 255A icc_max is not persistant to power cycle, just PWR_BTN off/on clears to default values.
the original software PowIRCenter should be able todo this, or there is a write protection enabled to prevent that.

edit: found the write to OTP function
data is written in the chip and is persistent.
but no to Rome work.

 

[Vladyslav Pantilimonov]

bad news:
have seen register 0x28 goes from F0 (240A) to FF (255A) icc_max.
i can only access the VRM with powered CPU.
so i power the board, press pwr_btn and changed registers to the 8144 file given from the BIOS,
but i can't get ROme to work.
unfortunaly the written 255A icc_max is not persistant to power cycle, just PWR_BTN off/on clears to default values.
the original software PowIRCenter should be able todo this, or there is a write protection enabled to prevent that.

edit: found the write to OTP function
data is written in the chip and is persistent.
but no to Rome work.

I guess (and only guess) that it must be not the current limits but maybe some feedback voltage adjustment compensation, or offset or overshoot/undershoot compensation.

Also, probably, it's more about IO core, not chilplets, since Rome stops on the memory initialization steps ("c0", "d0").

My 7F32 is well under current limits of the Naples generation, but still no started properly.

Also maybe there is updated VID table, etc.

The only way to know as we both guessing - having late rev. 1.1 board with working Rome support.

Then it's possible to see what exactly happened in the VRM firmware.

Obviously, this is only my thoughts, I do not pretend that it should be that way.

 

[RolloZ170]

I guess (and only guess) that it must be not the current limits but maybe some feedback voltage adjustment compensation, or offset or overshoot/undershoot compensation.

i have programmed all registers from VR update 8144, both VRM controllers. 35201&35204

My 7F32 is well under current limits of the Naples generation, but still no started properly.

EPYCD8 runs Rome with icc_max = 240A, so that can't be the issue.

 

[RolloZ170]

update:
got a Naples CPU, board still works with new VR update. have flashed from Vertiv 1.98 to new 12.xx.xx BMC AMI Firmware (EFI shell bmc_fw_update_uefi.nsh)
i updated the VRs for RAM also now(Rail1 icc_max 95A->125A), but still Rome not work.
there are 2 undocumented LEDs near the BMC LED, they lit up with Naples but not with Rome.

 

[Vladyslav Pantilimonov]

Do you have a POST card?

To see at what point it stops?

I use this one, it works ok by TPM port:

https://www.ebay.com/itm/286908803816

My Rome config freezes at "c0" or "d0", sometimes even at the "00".

 

[RolloZ170]

Do you have a POST card?

My Rome config freezes at "c0" or "d0", sometimes even at the "00".

have 460 and TL631 PRO, both
'00'
edit: but both card never worked on other motherboards, e.g. supermicro's, maybe both cards are defective ? don't think so.
board is a MZ31-AR0-00 (non HZ)

 

[Vladyslav Pantilimonov]

00
board is a MZ31-AR0-00 (non HZ)
View attachment 49354

I believe something is wrong.

If CPU isn't locked (it usually refuses to power off trough button or BMC in such case) it definitely should start to some point, I believe.

At least, mine starts to the memory initialization (according information in the internet by my POST codes).

Which POST card do you use?

 

[RolloZ170]

I believe something is wrong.

If CPU isn't locked

Rome CPU works on my ASRock Rack EPYCD8-2T
MZ31 work with 7401P (have soldered 32mb chip)

(it usually refuses to power off trough button or BMC in such case)

powers off as it should, 4 sec delay by pwr_btn

At least, mine starts to the memory initialization (according information in the internet by my POST codes).

c0 = OEM BDS initialization codes
d0 = CPU initialization error

Which POST card do you use?

have 460 and TL631 PRO, both
'00'

 

[Vladyslav Pantilimonov]

Rome CPU works on my ASRock Rack EPYCD8-2T
MZ31 work with 7401P (have soldered 32mb chip)

powers off as it should, 4 sec delay by pwr_btn

c0 = OEM BDS initialization codes
d0 = CPU initialization error

have 460 and TL631 PRO, both
'00'

I dunno that it matters a lot, but, such POST codes I had across all 3 motherboards I had dealt with.

All of them had the same behavior.

This is why I said that I believe that something is wrong in your case.

However, I can be wrong, obviously.

 

[RolloZ170]

This is why I said that I believe that something is wrong in your case.
However, I can be wrong, obviously.

works fine with 7401p, i could roll back to old VR version.

I dunno that it matters a lot, but, such POST codes I had across all 3 motherboards I had dealt with.

have you one working ? if not maybe you have one faulty part but not mobo.

 

[RolloZ170]

I dunno that it matters a lot, but, such POST codes I had across all 3 motherboards I had dealt with.

with Naples 7401P and TL631 i get displayed POST codes.
with Rome it seems platform reset is helt low (TPM header)
i guess there is some cpu sequence control need updated but i can't find a CPLD/FPGA chip.

 

[RolloZ170]

I dunno that it matters a lot, but, such POST codes I had across all 3 motherboards I had dealt with.

pulled the Rome out of the EPYCD8 and dropped into socket, good day.
but i flashed MZ31 to BIOS M15_R40 3.x by mistake, and now i get many POST codes stop by 'C0'

update: now stopped work again by flash other BIOS.
tried flash_R.RBU (selfmade, flash by BMC) result stop at code 'b8' ( Reserved for future AMI codes )
update:
have rolled back to stock 1.1 VR settings and got code 'd0'
update:
c0, d0, b8, it is not consistent.
i have to stop here because the IR35xxx have OTP2 and only 5 banks remaining from factory.
i have programmed three times and now have 2 banks left.

 

[Blackclaws]

Well I should have read this thread more thoroughly. I got myself the Rev 1 board, no HZ flashed the latest R40 bios on it and my Milan CPU 7663 won't post at all. I get persistent fanspin on the PSU when I plug it in and the BMC comes up but no fanspin on the CPU fan or any sort of signal that _anything_ has happened at all.

My board serial starts with 1749 so it might be no good at all to run anything _but_ Naples.

So I haven't read anyone in this whole thread so far saying they actually got Milan working only Rome or is there someone that actually got a Milan CPU going?

The main reason I got this board was the 16 slots for RAM on a single socket and the Rev 3 is just 3 times as expensive .... would be great if we could somehow solve this :/

This listing: https://forums.servethehome.com/index.php?threads/mz32-ar0-rev-1-3.40433/ gives me some hope its possible. They claim they made a Rev 3 board out of a Rev 1 board by some hardware magic they are known to do over there .... Scratch that.... That's an MZ32....

 

[RolloZ170]

My board serial starts with 1749 so it might be no good at all to run anything _but_ Naples.

So I haven't read anyone in this whole thread so far saying they actually got Milan working only Rome or is there someone that actually got a Milan CPU going?

i gave up on mine until new idea.
it is some change of VRM config by cpu type i didn't know how it work so far.
i need Rome/Milan compatible one to dump full VRM programming, currently i have only VR update data which is not required to run Rome.