Generally, this will not work. The electrical interface on the backend of QSFPP ports tends to be 4x10Gb bi-directional lanes, which then usually connects to a SerDes and/or ASIC. Again, typically, the lanes to the SerDes/ASIC needs to be clocked identically for the system to operate correctly.
A QSFPP to 4x10G SFPP break out cable can be thought of as breaking out those 10G lanes from the QSFPP port individually. Regardless of what the port is connecting to, the silicon behind the port is still expecting lanes of 10Gb. While I've seen gearboxes that switch between 1G and 10G lanes, I've yet to see it on silicon that is designed for 4x10G native.
LT;DR: No.