Thanks, for some reason I thought some QS variants wouldn't say Intel Confidential on them. Not sure where I got that from.
ES Xeon Discussion
- Thread starter britinpdx
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many seller show retail CPU but selling QS, you get a CPU with Intel Confidential.
intention is to hide the source of the QS/ES, if intel finds out he may get some penalty (3rd party/buyer is fine)
price is low, this model is single socket, low core count low TDP.Most of the others in this price range are marked as QS using similar photos.
Intel Xeon Gold 5411N LGA-4677 1S Server CPU Processor 1.90GHz 24-Core 45MB 165W | eBay
1PCS; 5411N. We are founded in 20 10, is a professional purchasing B2B & B2C tool in electronic components field. During the warranty period, we can help them repair for free. We will reply you in 24 hours and give your a satified answer.www.ebay.com
can be legit, If in doubt, ask the seller.
Does anyone who uses this kind of CPUs for LLM's have tips, which software stack is used to use AMX and other Features effectivly? Anyone using vLLM with Openvino and has tips how to get it running?
SPR 4th gen can be used with (unofficial Debug) BIOS 1.0 - but if you get a motherboard with BIOS 1.2 or higher downgrade is only possible by replace BIOS chip preprogrammed with BIOS 1.0 (soldering)
Supermicro runs Root of Trust Firmware, after modification re-sign by SM is required (they won't do for you)
there is a vulnerablility but you need deeeeeeeeep insights (NDA protected information)
X13SEM does not support Xeon Max. the CPU may start, but without HBM (not powered)
My friend successfully lit up a genuine 9462 with this board.and HMB is working on x13sem I also really want to experience the feeling of HMB, so I'm very curious about whether the
QYGG can be used normally. thanks
supermicro lists Xeon Max support on some motherboard but not X13SEM e.g.
ok is it POST and HBM is working: if you have any issues you can't ask supermicro, they will simply say "Xeon Max is not supported on X13SEM"
QYGG is not production stepping and do not work on any supermicro motherboards using latest BIOS.
if you want to run Intel ES CPU, avoid supermicro motherboards.
hello.
I saw a work in Chinese Internet,that is QYFS and supermicro X13SET-G and I would like copy it,because X13SET is only 2000CNY in goolfish.and the seller tell me his good could support SPR ES.I could only find another motherboard which is double price at least.And Pmem 300 series is avaliable.Is this work good?
and could 8*256Pmem + 8*16rdimm work,I heard some limit of RAM between Pmem,about their size,I mean if it must work when special rate,like 1:8, 1:16.
and I saw " if you want to run Intel ES CPU, avoid supermicro motherboards. "
emmm,it has some major BUG?
thanks.(sorry for my bad English)
I saw a work in Chinese Internet,that is QYFS and supermicro X13SET-G and I would like copy it,because X13SET is only 2000CNY in goolfish.and the seller tell me his good could support SPR ES.I could only find another motherboard which is double price at least.And Pmem 300 series is avaliable.Is this work good?
and could 8*256Pmem + 8*16rdimm work,I heard some limit of RAM between Pmem,about their size,I mean if it must work when special rate,like 1:8, 1:16.
and I saw " if you want to run Intel ES CPU, avoid supermicro motherboards. "
emmm,it has some major BUG?
thanks.(sorry for my bad English)
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SPR ES don't work, at least with actual BIOS. ( BIOS 1.0 debug/test BIOS is available for some models )
the earliest BIOS for X13SET i have does not support SPR D0 ES QYFS,
the BIOS with 5th Gen support does not support EMR ES A0, there is a workaround but supermicro X13 BIOS can not be modified.
Yes x13set-g is working, I actually have a few of them. They can use the ones you mentioned. If you need them, you can provide me with the contact information and I can sell them for you.
Supermicro has quite a number of preview motherboards (ES/QS). These version 1.0 motherboards are equipped with ES's BIOS, CPLD and BMC firmware. They can run CPUs with step 3 up to step 7. However, they cannot upgrade the firmware! This means that he can only use the 4th generation CPU of the es model.
this means you have to live with the bugs
there are no RelNotes for BIOS after 2.1
on the other hand, new BIOS lacks PMEM support.
Code:
2.1 (12/07/2023)
1. Updated AMI label to 5.32_EagleStreamCrb_0ACOR_099_Beta
for BKC WW47 EMR PV candidate.
2. Updated Eagle Stream Refresh Emerald Rapids Unified Patch
Engineering Release - 2023 WW47.
3. Added Rocky Linux and sles-secureboot OS into BIOS default
identical OS list.
4. Updated VROC SATA/sSATA/tSATA/VMD EFI driver to VROC
PreOS v8.5.0.1096 PC.
5. Added VROC on Demand driver support.
6. Updated the SUM OOB module to SMCOOBV2.00.21 to
support Redfish replace the display name feature.
7. Used PCIe ASPM Support (Global) to control ASPM(PCH), PCIe
ASPM Support(IIO), Native ASPM(ACPI) option.
8. Hid the "XPT Prefetch" feature in EMR CPU.
9. Supported VPD data of Broadcom Network Adapter.
10. Grayed out "Preferred DNS server IP" and "Alternative DNS
server IP".
11. Implemented BIOS setup keyword search function.
12. Fixed HostInterface On/Off stress test will drop in UEFI Shell
intermittently.
13. Changed the FixedBootOrder BBS Group define start from
COMMNE00 not COMMNE01.
14. Default disable OOB send replace DisplayName feature to
avoid that the SUM OOB test fail problem.
15. Rebuilt variable BootOrder according to previous boot if
variable Boot0000 is created during OS installation.
1. [SmcUefiBootsOptionRedfish] Made sure to assign unique ID
for NVME device.
2. Fixed the Secure Erase malfunction.
3. Fixed the issue where the system could get stuck at BIOS POST
Phase after platform warm reset with USB4 devices.
4. Cleared RTC clear flag and IPMI RTC clear flag individually to
prevent "Setup default has been loaded" from displaying
during next boot.
5. Fixed the issue where the BIOS cannot go into setup menu
after editing setup default value by AMI BCP tool.
6. Resolved IPV6 "Preferred DNS server IP" and IPV6 "Alternative
DNS server IP" which were not displayed correctly on the BIOS
setup.
1.5 (10/27/2023)
1. Updated AMI label to 5.32_EagleStreamCrb_EMR_0AOR_093.
2. Adjusted the position of FwCapHdr to the front of FV_MAIN to avoid secure flash and boot guard
sign fail.
3. Exposed “Page Policy.”
4. After using SUM to load the BIOS default, BBS can be restored to default.
5. Updated PCIe Leaky Bucket Expected BER item default value.
6. Updated Seamless MCU capsule revision to 1.0c for PLR4.
7. Fixed the incorrect IPv6 information and corrected the string issue in “Preferred DNS server IP” and
“Alternative DNS server IP” when BMC sent an invalid IP.
8. Used corresponding HBM SMBIOS type 17 device locator format (UP: HBMIOx, DP/MP:
Px_HBMIOx).
9. Used corresponding HBM memory format on BIOS setup (UP: HBMIOx, DP/MP: Px_HBMIOx).
10. Modified ME version strings and removed the “Manufacturer ID” string.
11. [SmcGetSetSBkeys] Fixed the issue of Preserving Secure Boot Keys.
12. Resolved an issue where the system would hang when restoring the Secure Boot keys.
13. Fixed the issue when the system hangs on ACPI enable if the CPU core number is more than 256
and set max performance.
14. Fixed the problem that httpboot boot option cannot be created.
15. Resolved the “BMC LAN Selection” setup item that differed from the “LAN selection interface”
under BMC WEB GUI.
16. Resolved the issue where the IPv6 address was still displayed during the EarlyVideo stage when
‘IPv6’ was disabled.
17. Resolved the issue where IPv6 “Gateway IP” was not displayed correctly on the BIOS setup.
18. Resolved the issue where the system would encounter ASSERT while executing GetHIDevicePath
function.
1.2 (03/23/2023)
1. Updated Intel BKC 2023_WW09, Intel RC Version 9409.P31 MR2, and HBM PV.
2. AOC-A25G-i2SM and AOC-A25G-M2SM SMBIOS report incorrectly when located at Rear I/O
AIOM1
1.1a (3/3/2023)
1. Updated Intel BKC 2023_WW07, Intel RC Version 9409.P19.
2. Exposed and adjusted the MMRS item to fine tune Gen5 performance.
3. Fixed the FWTS and WHQL fail issue.
4. Used Supermicro’s defined GUID for compatibility between SuperBIOS and AMI.
5. Fixed Type 17, which did not follow SPD Spec MemoryChannelBusWidth.
6. Exposed the CPU feature, "Optimized Power Mode."
7. Updated the SATA SGPIO Mode option strings for all SATA configuration menus.
8. Followed BIOS Setup Template v1.1 to hide the “UPI3” feature in UP projects.
9. Hid the "Homeless Prefetch" feature.
10. Updated SPS 6.0.4.25 2S PV Hotfix Release for EagleStream platforms.
11. Corrected gPayloadOffset definition to fix the inability to successfully program NVRAM with AFU
utility
12. BIOS POST Progress Support requirement in Redfish.
13. Followed BMC_Network_AOC_Monitoring_Spec_v2.2 to avoid sending the AIOM/AOC IO Module
LAN MAC to BMC.
14. Removed the "Supermicro Security erase" page from HII format.
15. Followed the setup template to expose the
Consistent Device Name Support” feature when SMC_CONSISTENT_DEVICE_NAME_SUPPORT is
enabled.
16. Updated the AST2600 VBIOS and VGA UEFI driver to 1.13.01.
17. Created UEFI OS name on the boot option for removable devices.
18. Converted "Supermicro Security Erase Configuration" page to JSON format.
19. Added SecureBoot Database to meet the Redfish specifications.
20. Created SmcKMSOOB to prepare the VFR/UNI and to create the ConfigAccess Protocol which will
be used when transferring files to JSON format. Commented out the extra “Supermicro KMIP
Form” when using the SUM utility to generate BIOS config file.
21. Transferred Supermicro HTTP BOOT MAIN" page (HTTPS TLS certificate upload/delete via
SUM/BMC) from HII to JSON format.
22. Fixed the AFU return error that appeared when using /N or /clnevnlog commands.
23. Made Enable the default TOKEN "SMC_HECI_HIDE_DELAY"( HECI-x hide delay ) for all projects to
fix BSOD issue.
24. Exposed the "Equalization Bypass To Highest Rate" feature.
25. Automatically hid the ADDDC Sparing feature with x8 width DIMMs.
26. Exposed "CXL Type 3 Legacy", "CXL Security Level" and "CXL Header Bypass" features for CXL.
27. Revised the code for NVMe PCC init.
28. Updated PCIe riser card support to include CBL-ASMC-1321DM5YP.
29. Enhanced the BIOS setup string and SMBIOS for different system configurations.
30. Fixed the issue where M.2 devices did not appear when setting up the VMD mode from PCH.
31. Enhanced front IO naming on BIOS setup.
32. Enhanced SMBIOS data when installing AIOM card.
33. Swapped the Slot ID for front IO AIOM slot.
34. Enhanced reporting SMBIOS type40 data.
35. Revised the Legacy intergroup that can’t be listed in order.
36. Fixed the WHQL HSTI Rollback firmware error.
37. Fixed HTTP/HTTPS boot failed.
38. Fixed system hang at 0xEE if the COM1/COM2 console redirection is disabled.
39. Updated binaries for SMCOOBV2.00.17.
40. Fixed the memory serial number of SMBIOS type 17, which did not match the memory DIMM bar
code.
41. Fixed the NVMe hotplug malfunction with BPN-NVMe5-F418-B6S6.
42. Masked ASPEED onboard VGA PCIe correctable error.
43. Corrected SLOT BDF for CPU port PE5.
1.0 (09/21/2022)
1. First release.to be fair, if you want to use PMEM with gigabyte C741 motherboard you can not use latest BIOS too, PMEM support is removed because Intel discontinued the Optane Persistent Memory 300 Series and the entire Optane product line.
The most interesting part is that in the latest R12 BIOS (the latest BIOS I have tested), Gigabyte (MS03-Ce0) did not remove the support for PMEM
in the BIOS， which means that users can still use the fourth generation along with PMEM .I am interested that why SPR has 12 steps. Are D0 steps ES (like QYFS) have some major bug?or just the Cost or Yield problem
SPR D0 was close to PRD state, you can imagen if you look at the clocks, but high IDLE package power because of 4 tiles using 10 EMIBs.
intel decided to re-design silicon, to get more chips out of wafers and make some things better.
MCC (non chiplet) was forced to reduce IDLE package power, the begin of EMR dual chiplet (3 EMIB) design.
not corecct.
start at 806F0, current 806F8 is 9 steps
but XCC and MCC have different stepping names, e.g. D0 vs R0.
AMD EPYC have lower stepping count because the have chiplets in any case.
edit:
Stepping E0,E2,E3,E4;E5 share microcode(MCU is for cores only)