Epyc Rome core configuration (7302)

[FaSti]

This STH article (https://www.servethehome.com/amd-epyc-7002-rome-cpus-with-half-memory-bandwidth/) gives a good overview over Epyc Rome CPU architecture, but I need more spesific Information about the 7302. AMDs website says, the memory bandwith of this processor is 204.8 GB/s. As this is the same number as for the 64 core model, I gues all 4 quadrants must have a die so that all 4 infinity fabrics of the I/O die can be used. Wikipedia says that the Processer has 8 CCXs with 2 cores each and that the CPU has 4 CCDs, so I gues every quadrant must have a die with one CCD each and every CCD must have 2 CCX with 2 cores each like shown in the diagram I made. 2 x 2 x 1 x 4 = 16. Is this correct?

 

[RolloZ170]

L3 cache size / 16 = num of CCX
with 128MB L3 this is correct. must not 4 CCD, but i think AMD does only so.