Where's all the lanes?
Still the same as H11DSi, lots of CPU PCIe lanes wasted
not really. they squeezed in an entire extra x16 slot vs the H11DSi
on dual socket EPYC configurations. 64 lanes from
EACH CPU are used for CPU<->CPU communications. so dual socket still only exposes 128 lanes total to peripheral devices. Some systems can be reconfigured to reduce CPU<->CPU lanes to expose up to 192 lanes, but I'm not sure this board can do that.
2x EPYC = 256 lanes total
-64 from each = 128 lanes left
-48 for 3x PCIe x16 = 80 left
-24 for 3x PCIe x8 = 56 left
-16 for 4x PCIe x4 internal NVme = 40 left
-4 for 1x m.2 x4 NVme = 36 left
and going to assume that USB/SATA/10GBe are all using some lanes too.
yeah, they could maybe squeeze some more lanes in to make it like 6x x16 slots, or a second m.2 port or something. but it's not egregious and there are probably other factors like board layout and the price point they are trying to hit.