DDR5 ECC SO-DIMMs availability

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pimposh

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Nov 19, 2022
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Anyone seen DDR5 ECC SO-DIMMS (4800+) 32/48GB modules available somewhere ?
Just got my new node delivered, unfortunately by choice of design although it's W680 based it is using SO-DIMM form factor.

This "on-die ecc" effectivelly messes up searching engines and i got troubles finding real ones.
 

BlueFox

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BlueFox

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All DDR5 has on-die ECC, so you can effectively ignore that as a "feature". If it didn't, it wouldn't be DDR5. Manufacturers don't call that ECC memory...they call it DDR5. ECC is still dependent on extra data lines to the CPU.
 

pimposh

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That is what i knew. So for example Kingston memory modules i linked above - are NOT ECC in contrary to product description in datasheet. Correct ?
 

pimposh

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I'm dumb sorry. I didn't noticed marked line. But... given density shouldn;t it be 80 bit in this case?

 
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twin_savage

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Try "EC8" to restrict to the ECC we are all used to.
Technically there is no such thing as EC8 DDR5 UDIMMs according to JEDEC... even though we can obviously see 80 bit widths on these UDIMMs based on package count.
If you look at socket pin outs it would appear AMD AM5 can't use EC8 but Intel LGA1700 can. AM5 is relegated to EC4.
 

twin_savage

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If you look at the names of the pins on an AM5 socket, there are only 4 check bit pins per 32 bit subchannel, but LGA1700 has a full 8 "extra" pins dedicated for each 32 bit DDR5 subchannel (conveniently named something completely different than what AMD calls them).
This means AM5 can't actually use EC8 because it doesn't physically have enough traces to connect to it, but LGA1700 does even though EC8 UDIMMs are not part of the JEDEC DDR5 memory spec.
If you look at SMBIOS data on each respective platform, it seems to corroborate this.

Intel has gone outside of JEDEC in the past though, they are using MCRDIMMs which are not a JEDEC spec, so it seems plausible that Intel is going above and beyond here. I'm just surprised that the memory producers are making DDR5 UDIMMs with the full 80 bits worth of chips on them even though JEDEC only calls for 72 bits.
 
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pimposh

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One more thing.

Given on-die-ecc existence is it expected to have less errors to be corrected by in-line ecc ? And if so, in-line ECC lost bit of it's value ? Seems valid right ?
 

twin_savage

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Given on-die-ecc existence is it expected to have less errors to be corrected by in-line ecc ? And if so, in-line ECC lost bit of it's value ? Seems valid right ?
It's hard to say, I've heard part of the reason for adoption of inline ECC is so that the manufactures can use lower quality DRAM dies with higher error rates which might cancel out some of it's benefits as compared to previous generations of memory.
One thing inline ECC doesn't do that "real" or sideband ECC does is inform that an error has taken place and this is important to know.
 
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