Do you have temp measurements prior this change to compare results to (under the same stress test conditions)?
What are recommended reasonable (and max) operating temps for those VRMs?
For example lots of MOSFETs are designed to operate long-term on up to 90-100 C temps, if you are well below 80 degrees (although depends on sensor position) then all this upgrade hardly has impact on VRM life durability/degradation.
With the original heat sink, comparable ambient temperature (75F), and identical stress test (standard s-tui/stress-ng all threads test), CPU VRM temperatures reach 79-83C after 25min. So the improvement here is maybe a few degrees. I was unable to find formal specs on these VRM chips (I am sure they are somewhere) but the recommendation from several people on this forum is that the VRM temperatures should be less than 80-90C with anything greater than 100C causing throttling.
@RolloZ170 provided a particularly insightful plot showing the relationship between current and VRM temperature
here.
It is interesting to note that the experiments shared by the seller show CPU VRM temperatures around 65-66C. See the forum threads located
here and
here for details. But the test configuration and timing used to produce these temperatures are not clear to me (perhaps my Chinese translation is off).
So yes, for this 2mm thermal pad scenario, this exercise indicates that the magnitude of improvement is not significant enough to justify the time/money/effort (and risk of damaging the board). The 1.5mm thermal pad may produce an additional ~5C drop and maybe with more conductive pads we could achieve another ~5C drop. But is this worth the effort? Probably not especially for my scientific computing use case that involves short bursts of max CPU load. I bet we could get even better results with a 1mm thermal pad, as was shipped with the heat sink, but I think the danger of shorting out components is too high as decribed by
@twin_savage.
So why did I do this? I am interested in upgrading several dual socket nodes in my cluster to 64 core Rome CPUs once they at the $400-500 mark in the second hand market, which seems to be on the horizon. These CPU's can yield VRM temperatures that exceed 90C, and this case could benefit from a better heat sink. The experimentation shared in this thread is a relatively cheap ($45 for heat sink + cost of thermal pads) way to gauge the utility of this custom product for this future potential upgrade. I also learned a lot about thermal pads, working with springy screws and regulating expectations from custom solutions. And I didn't damage my board (yet).
Also it's normal for VRMs of CPU1 and CPU2 to have different temps because of VRM locations (e.g. hot exhaust from CPU1 blows directly onto VRM from CPU2 whilst VRM for CPU1 is on air inflow and has no such inflow of hot air).
You might benefit from having more customized time-line graph with min/max for just desired VRM segment over say 1 hr of stress benchmark.
I don't see material differences for between 1 and 2 for VRMCPU and VRMSoC but only 10+ C degrees between VRMP1 and VRMP2
My cluster is tailored for a research office setting requiring noise to be at a reasonable level. Therefore, vertical full tower cases with excellent airflow are used that accommodate large and quiet Noctua coolers. These coolers have fans that blow toward the top of the case which reduces the temperature differences commonly observed in a 2u/4U chassis with high rpm fans blowing toward the back.
Thicker thermal pad means worse thermal conductivity between CPU lid and metal of heatsink, therefore negating desired effect between original factory-mounted one and custom (although both have even surface therefore should have same clearances also perhaps apart of difference arising {a} from using different rotation strength/pressure/springs for mounting screws/bolts and {b} considering the fact of fatter weight {more heat absorption} + effect of directly-mounted cooler vibration {dynamics} and size {VRM height} difference resulting to rotational momentum pressure if MB is mounted vertically {standing position, not laying flat})
Agree with one modification. Changes in thickness lead to a changes in thermal resistance (degrees C/W = thickness/conductivity/Area) whereas thermal conductivity is a material property that is not a function of thickness assuming all other variables are held constant.
Just a thought/experience sharing: In my practice to eliminate/reduce risk effect of different heights for surface-mounted electronic components (circuit shorting if spring squeeze makes a physical contact between component and metal surface of heatsink) I would normally work on heatsink with file or drill (since most home users wouldn't have proper face mill normally available on industrial metalworks premises {although small diameter sometimes is a problem there too}) - making height/distance more even which allows minimization of thermal conductivity loss accounted for thermal paste/pad.
File approach doesn't make much sense in your case (since this is just one component, not a lined array of those, plus working with file on metals with higher viscosity like copper or aluminum requires extra effort and tool maintenance) but drill would be much simpler (drill bit for hard metal because entry surface angle shouldn't be so sharp, drill for softer materials will give too uneven/angled hole surface) without making a hole (to minimize change in mechanical folding resistance/integrity) but only to lower level for half a millimeter, not of too large diameter but sufficient to compensate some variance in mounting granting enough clearance around it (avoiding risk of misalignment).
Thank you for sharing this. I will keep this in mind for future work.
