The absolute slam dunk would have been if AMD Ryzen Threadripper Gen 2 went to 1 DIMM per channel with RDIMM support.
Wouldn't that be 1 channel per die instead of 1 DIMM per channel?
Also, I don't know if your RDIMM wish is even teorically possible... ...unless you know something we don't, which is highly probable
The Control part of the Bus has different wiring to the DDR Slots so they connect to the buffer chip in the module instead of directly to the DRAM chips (Albeit you can make a hybrid Motherboard that supports both UDIMM and RDIMM, like Supermicro did for at least some of their Xeons E5 platform). If such wiring is not present in the current Motherboards, even if AMD decided to allow ThreadRipper to also be able to use RDIMM, you would still need a new Motherboard. Perhaps by the same reason it is impossible to go down to 1 channel per die with the same amount of slots in a backwards compatible manner, the Motherboards aren't wired that way. I suppose that it should have been possible to implement such solution if AMD redesigned the ThreadRipper package to change how the dies are wired to the memory pins.
As much as I love Zen and all the praises that AMD is getting, I still think that AMD take on its platforms is like an afterthough (Like AM4 getting only 24 PCIe Lanes instead of the full 32 that Zen has, one of the mains reasons why I can't stand it. Not using the built in 10G MAC is also a capital sin, albeit after some research it seems that the 10G PHY are rare. Still waiting to see what a fully geared Embedded Ryzen V1000 used as pure SoC scaling up to mATX can do...). Wouldn't it have been better to get ThreadRipper running as a 100% compatible subset of EPYC? I mean, some type of platform flexibility, like you had in LGA2011-3, where you could plug a single Xeon E5 in a Dual Socket Motherboard and get it to work but with half the Motherboard I/O dead, or with ECC support depending on if you are using a Core i7 or Xeon. I think I have hear about a single Core i7 being usable on Dual Socket Motherboards, but don't recall in which generation that worked (Yes, I know, that is a last resort measure and not the intended way to use the platform).
For example, suppose that any SP3 Motherboard has its critical I/O coming from the first and second dies, so that any Motherboard could boot with the original ThreadRipper. The third and fourth dies are non critical expansion. If in a Motherboard intended for EPYC you plug a ThreadRipper, it works but you miss third and fourth dies I/O including Memory Slots, but if you do it the other way and plug a fully enabled EPYC in a scaled down ThreadRipper Motherboard, you get the current ThreadRipper 2.0 with two pure compute dies with no I/O.
Somehow it seems that either AMD never had that plan, or that they couldn't even plan for it because it didn't expected a product like ThreadRipper.
