AMD EPYC June 20, 2017, Threadripper and Vega at Computex 2017

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DWSimmons

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Apr 9, 2017
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Couple things I see/heard

The TDP of Threadripper as far as I've seen is 140w. The ARK only has up specifications to I-9 7900x and it's 10 core. Patrick summed itt up here.




That's efficient for the thread count. The chipset is huge and pci-e lanes count high so the boards will be large - likely no such thing as mitx work lots of eatx varieties. I can't see any downside to a physically larger chipset. TSMC tooling upgrades are well known at this point and the Threadripper is 16nm (as is all NVidia). I suspect the chipset size partly had to do with the limitations of TSMC. This also suggests that AMD efficiencies and/or upgrades already available as soon as TSMC gets their 12nm act together.

AMD made it clear that this is not Ryzen9. I have not seen a Threadripper stack graphic yet. I suspect that is actually a quad-quad core. Specifically, two 1800x fused with infinity fabric. Remember that the 1800x is actually two quad core. Bolting two 1800x together would reduce the production to one die and then everything is binned and reused from there. (This has also been alluded to in another product release of multichip on one socket.). While AMD may not have had any control on die size, they have had control on thread queuing and efficiency algorithms on the chipset. In other words, if they can't go smaller or faster, they can parallelize.

This has significant ramifications for virtualization and containers. How much subscription/oversubscription can you squeeze had been a consideration for years now. A lower price especially in TCO for the same subscription is an attractive proposition.
 

markarr

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That graphic shows 44 when all of the AMD parts have 64 lanes. There is still a lot of information that AMD did not release yesterday, will probably have to wait till June 20th. AMD seems to want to not call threadripper Ryzen 9 as it wasn't mentioned in the "announcement".
 

DWSimmons

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That graphic shows 44 when all of the AMD parts have 64 lanes. There is still a lot of information that AMD did not release yesterday, will probably have to wait till June 20th. AMD seems to want to not call threadripper Ryzen 9 as it wasn't mentioned in the "announcement".

What you said. The chart is from a WikiChip leak pre-Computex 64 lane announcement.

Edit to add:. I'm under the impression from ARK that the Intel numbers are total, if true, that would make an apples to oranges comparison.
 

markarr

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44 lanes is the amount of lanes remaining. 64 lanes is the total amount but 44 lanes is the amount that can be dedicated for multiple graphic card configurations. The other 22 lanes are dedicated elsewhere.
60 will be allowed from the cpu to I/O, the remaining 4 go to chipset from yesterdays announcement.

At today’s press conference, AMD has confirmed that the 16 core processor will for most purposes be half of an Epyc processor. This means that the two die MCM chip will feature 4 DDR4 channels and a whopping 64 lanes of PCIe, with all 64 lanes being enabled for all ThreadRipper SKUs. This will be broken up into 60+4: 60 lanes directly from the CPU for feeding PCIe and M.2 slots, and then another 4 lanes going to the chipset (with an undisclosed number of lanes then coming off of it) to drive basic I/O, USB, and other features. AMD seems to be particularly relishing the point on PCIe lanes in light of the yesterday’s Intel HEDT announcement, which maxes out at 44 lanes and no chip below $1000 actually has all of them enabled.
 
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Jeggs101

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I want Intel cores but 64 PCIe. That'll make mobos cheaper since they don't need PCIE switches.
 

DWSimmons

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I'm very curious how people are using 40+ lanes. I know there are many ways, I guess my question is it graphic cards or storage or something else or a combination of factors.

Partly, I'm thinking AMD is clearly willing to attack the lower end server market with prosumer gear, even if it means cannibalizing their new server offerings.

I can't imagine the sub 5K academic, content creators, hardcore enthusiast market can compete with the enterprise purchases. Maybe this the old school, get-in-when-they-are-small marketing or maybe this is the trend toward not-cloud group. Again with TSMC, this might also be a production volume issue too. Maybe, they aren't ready to go big quite yet. Either way, props to Dr. Su as she appears to have AMD pointed toward viable competition.
 

DWSimmons

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@DWSimmons NVME + GPU shreds PCIE lanes. Adding more NVME instead of SATA is a driver.
I get *how* one does it. What is the use case for stacks of nvme and GPU. If it's ML then you don't need stacks of NVME, if it's storage or web services, you done need GPU. If it's an attempt to jam so much hardware into one box in order to do both, I have a hard time coming up with a business use case where single point of failure for a super box makes sense. I'm sure they are people out there who might bump against this but that goes back to my original point, what is the market they are a value proposition for.
 

MiniKnight

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I get *how* one does it. What is the use case for stacks of nvme and GPU. If it's ML then you don't need stacks of NVME, if it's storage or web services, you done need GPU. If it's an attempt to jam so much hardware into one box in order to do both, I have a hard time coming up with a business use case where single point of failure for a super box makes sense. I'm sure they are people out there who might bump against this but that goes back to my original point, what is the market they are a value proposition for.
...but 2x GPUs is 32 lanes, too much for midrange Core-X. 1 GPU + 2 NVME (raid 0) + 1 40GbE adapter for network storage = 32 lanes.

2 GPU + 2 NVME + 1 NIC = 48 lanes.
 
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DWSimmons

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I would use a setup like this:
4x x8/x16 for nvme cache devices
1x x8 sas hba/raid controller
1x x8/x16 for networking (40/50/100 gbe or fdr/edr infiniband)
Here's a business use case I can see. The demands are low enough not to warrant server grade but high enough to use what's available. My gut says that the single socket Epyc will address the next step up an future proof for those that are in - what I see as a small - niche. At STH, it literally is the niche hence me asking.
 

Patrick

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The local RAID 0 cache I have heard as being popular for big video files. I know a few folks doing 360 video and that makes editing manageable.
 
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Mam89

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All I keep coming back to is ecc support on Theadripper. If you can stack 16 server sticks of ram into these things and load them with nvme+ decent hbas these could be chopped up nicely for cheap hosting boxes. The core clock would make them great for game hosts or other single thread intensive virtual boxes.
 

DWSimmons

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All I keep coming back to is ecc support on Theadripper. If you can stack 16 server sticks of ram into these things and load them with nvme+ decent hbas these could be chopped up nicely for cheap hosting boxes. The core clock would make them great for game hosts or other single thread intensive virtual boxes.

 
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Klee

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I heard that one of the 16 cores , do not know 1998 or 1998X, will retail for $849.00.:)
 
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BobbyB

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Since Threadripper is closer to release than Epyc, I wondered if X399 will be useful for a cheap(er) server platform with 16 cores.
According to this korean interview - Google Translate - linked in an OCN thread, it appears Threadripper has no buffered nor LR-DIMM support. Thus I guess same as R5/R7 ECC is still in unbuffered mode and half-support (not validated in AMD testing).

Also interesting from the article
Q5. Can Epic be used on an X399 motherboard?
A5. The packages and sockets of Epic and Rizen Thread Ripper are similar in appearance but not electrically compatible. Cross platform use will not be possible.
So there are two versions of SP3 socket I guess...

Here's hoping 1socket Epyc is affordable and stays above 3Ghz base frequency in 16c form. Memory will still be more expensive than the CPU/barebone system anyway, but competition is good.