AMD EPYC Genoa Gaps Intel Xeon in Stunning Fashion

zir_blazer

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Dec 5, 2016
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That entry level 1083 U$D EPYC 9124 seems... decent. 16C, 3.7 GHz for 1083 U$D with the beastly I/O of the Genoa platform, could make a viable ThreadRipper before ThreadRipper. I wonder how the 1P Motherboards looks.
 

pututu

Member
May 7, 2016
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I'm guessing the motherboard cost will go up to support pcie5 and ddr5, like the ryzen 7000 series, at least during the initial release until these features become mainstream soon. Anyway, for enterprise customer, usually it is the total cost of ownership over the life cycle of the system that matters more than the initial investment cost. Nice to dream of having such a system though.
 

alex_stief

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May 31, 2016
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Quick questions about the connection between CCD and IOD. It looks like AMD reworked that compared to Milan. Particularly the part where SKUs with only 4 compute dies *can* use two of the GMI3 links instead of just one
1) Will this apply to all Genoa CPUs with 4 dies? Or are there some cut-down versions with only one GMI3 link per CCD?
2) What's the theoretical bandwidth of these GMI3 links? Or more practically: are 8 GMI3 links enough to match the memory bandwidth of 12xDDR5-4800 for reads? It would suck having to buy the 96-core parts just to utilize the full memory bandwidth
 

mirrormax

Active Member
Apr 10, 2020
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That entry level 1083 U$D EPYC 9124 seems... decent. 16C, 3.7 GHz for 1083 U$D with the beastly I/O of the Genoa platform, could make a viable ThreadRipper before ThreadRipper. I wonder how the 1P Motherboards looks.
we can hope that someone brings out a workstation epyc board this gen, dont have my hopes up high though.
stuff like s3 sleep proper amount of usb etc would be sweet
 
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Spartus

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Mar 28, 2012
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Toronto, Canada
we can hope that someone brings out a workstation epyc board this gen, dont have my hopes up high though.
stuff like s3 sleep proper amount of usb etc would be sweet
I'm having the same thoughts and concerns.

I could maybe see a single socket board thats usable for workstations, potentially not even sized for all 400W, but I can't see a 2x400W 24 memory channel workstation existing at all. Which is a shame, I would be pushing that so hard.
 

Patrick

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Dec 21, 2010
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'gaps'? Is 'gap' a verb now? Yeesh.
I took a bit of liberty on that one, but here you go


Needed something with a "g" to go after Genoa and that was short since it was a long title already.
 

alex_stief

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May 31, 2016
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By the power of Cunningham's law, I will attempt to partially answer my own questions.
From the slides, it appears that the bus width of a GMI3 link is still 32 Byte for read (16 Byte for write). Just as in previous gens.
And the frequency is stated as "1.8GHz max". No idea what to make of "up-to-36Gbps, 20:1". Can anyone enlighten me on that?

If we roll with 32 Byte bus width and 1.8GHz, that's 57.6 gigaByte/s of read bandwidth for a single GMI3 link.
230.4 GB/s for 4 links
460.8 GB/s for 8 links
691.2 GB/s for 12 links

The theoretical memory bandwidth of 12xDDR5-4800 is 460.8GB/s. What a coincidence.
By my math, 8 GMI3 links would be just enough to match the full memory bandwidth, at least for reads.

The first question remains though. The article states "The 4x CCD variants (up to 32 cores) have an interesting trick where they can get 2x the links to the IO die per CCD"
I am stumbling over "can" here, which also appears in the AMD slides. Are there Epyc 9004 CPUs with 4 CCDs, but only one GMI3 link per CCD?

I'm gonna take a wild guess here: the CPUs with only 64MB of L3 cache total have one GMI3 link per CCD.
 
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