2666 R2 or 3200 R1 RAM for Naples/Rome EPYC ?

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NumbersGuy

New Member
Jan 18, 2022
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Hi.

I'm building a 32 core EPYC server for number crunching. The algorithm is highly parallel and memory bandwidth constrained. I'll be starting with a 7601, but will probably upgrade to a 7002 processor when the used prices fall a bit.

The motherboard will allow me to overclock the memory. I have the choice of buying 2666 MHz 2 rank memory or 3200 MHz single rank memory for about the same price.

Which memory will give me the highest bandwidth with the 7601 ? How about when I upgrade to a 7002 ?

Thanks
 
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moep

New Member
Jan 2, 2022
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Did you had a look into AMDs memory guide for Naples and Rome?

As far as I can see 8x SR RDIMMs @2666Mhz per CPU should provide maximum memory bandwidth with Naples (DR seems to be limited to 2400Mhz and thus performs worse).
With Rome and a Motherboard that supports EPYC 7002 memory speeds you could run your RDIMMs at 3200Mhz (in supported configurations, see memory guide linked above), which should perform significantly faster than 2666Mhz.

So i guess with Naples you should stick with SR memory and with Rome you probably want something clocked at 3200Mhz. If I haven't missed anything, this should be an easy decision between the two options.
 

UhClem

just another Bozo on the bus
Jun 26, 2012
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NH, USA
It depends ... ("What else is new?" :))

I was recently trying to get my head around the single- vs dual-rank (DDR4) thing, and eventually realized that the question gets complicated when you introduce "highly-parallel" into the mix. There appears to be a "cliff effect" regarding ranks and banks and streams. See [this post] (from a true authority on the subject). In your case, what you gain from higher memory speed (but single-rank), you might lose (drastically) beyond a certain threshold # of parallel cores accessing (vs. lower speed dual-rank), for a specific workload profile. The devil IS in the details.

Further research is warranted, before you commit.
 

NumbersGuy

New Member
Jan 18, 2022
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Did you had a look into AMDs memory guide for Naples and Rome?
I hadn't. Thanks for the links.

As far as I can see 8x SR RDIMMs @2666Mhz per CPU should provide maximum memory bandwidth with Naples (DR seems to be limited to 2400Mhz and thus performs worse).
With Rome and a Motherboard that supports EPYC 7002 memory speeds you could run your RDIMMs at 3200Mhz (in supported configurations, see memory guide linked above), which should perform significantly faster than 2666Mhz.
I see that.

So i guess with Naples you should stick with SR memory and with Rome you probably want something clocked at 3200Mhz. If I haven't missed anything, this should be an easy decision between the two options.
yes, especially because the 3200 MHz memory is single rank.
 

moep

New Member
Jan 2, 2022
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The devil IS in the details.
they can compete because at Dual Ranked memory one rank can tranfer data while the other decodes the rows.
You're both right. I was referring to the AMD documentation, which only talks about a theoretical bandwidth. AMD is for sure making some (over-)simplifications here, i should have mentioned that. In practice, the picture might be a bit different and can differ for different use cases.
 

NumbersGuy

New Member
Jan 18, 2022
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I was referring to the AMD documentation, which only talks about a theoretical bandwidth.
AMD makes it very clear that single rank memory is better for memory bandwidth constrained application, such as CFD work.

Memory Bandwidth Sensitive Workloads
Memory bound workloads will benefit from the maximum available memory speed. This can be
achieved with one2666 MHz DIMM per channel in a single slot per channel platform.This
configuration would be beneficial in memory bound high-performance computing (HPC)
workloads such as:computational fluid dynamics (CFD), weather modeling, crash simulation,
and oil and gas (O&G) exploration.
The only way one can achieve a memory speed of 2666 MHz is with single rank memory. It makes sense that single rank memory will be faster because dual rank memory will need 2 chip selects to read both banks. One chip select for the first bank and a second chip select for the second bank.