1. no bifurcation support in current BIOS (or at the very least it is hidden/no menu for it yet)
2.
3. it does support 48GB DIMMs out of the box... sadly 48GB ECC DIMMs aren't very available yet to test though
4.I assume it does (currently running 96GB), but their doesn't seem to be any way to...
Thank you for sharing this! I didn't know this was possible.
Does Mech/LLC overclocking work? it looks like your running at 2200MHz, if you could bring that up the memory performance would dramaticaly improve.
The normal W3400 processors run their LLC mesh at 2500MHz but the BIOS allows it to...
After being disappointed with the complete lack of higher density XMP RDIMM kits available I broke down and bought some normal 4800MHz 64GB Hynix sticks; turns out the 4800MHz server stuff will overclock just fine as long as you can cool it, I'm running DDR5-5945MHz 34-38-38-96 timings @ 1.35v...
The FTL can be thought of as a dynamic LUT that changes based on inputs (many of which are unknown to consumers), this is a useful way to understand what the FTL is doing. This is how the FTL is thought of during raw NAND data recovery after a controller failure, the FTL is "frozen" into a...
FTL as in the flash translation layer in SSDs; it is an ever changing lookup table that maps logical blocks to NAND cells. It was the cause of complete SSD failure during power loss in many SSDs awhile back because it would get into some kind of undetermined state after a power loss and all your...
I'd try taking the battery out and reseating it; might be a bad contact with battery but likely it's just a drained battery.
It's not that bad, the worse thing you'll experience is loss of BIOS settings after removing power from the machine.
type in "https://192.168.1.13" to get in to ipmi in the browser, without the https it won't resolve. same thing happened to me.
you're battery voltage is low, mine is showing 3.136 v, this is probably the cause of the red/orange flashing led.
The symptoms of SSD NAND cell charge decay are typically severely reduced read speed for the affected cells long before any data loss occurs, assuming we're talking about MLC/TLC/QLC/PLC (basically any SSD with a controller with sample NAND voltage to discriminate charge, some very early SLC...
The blog thoroughly goes through the write hole phenomenon on hardware/software raid, how BBUs were adopted for the former and how they only protect against power loss but not OS or firmware crash; and furthermore what can be expected after such an event.
The guy seems very knowledgeable as I'd...
It is true that the hdd itself will assign ecc per 4k block, which is all the more great. When I mentioned at the block level earlier I was referring to parity between entire blocks within a RAID set as opposed to ECC within a block that is deposited by the hdd's controller.
My earlier comments...
Read the summary and para above in this link:
https://www.klennet.com/notes/2019-07-04-raid5-vs-raidz.aspx
My gripe with ZFS in this instance isn't with the rate at which the file system tends to fragment files, it is that there is no in-place recourse to defragment. I'd prefer to get stressful...
This is very true, these functions could be included in that analogy to drive it home further; none of these RAS features belong in the kernel, they should be accomplished at a lower level.
I suspect the memory RAS features were initially implemented at a lower level in hardware for performance...
ReFS with data integrity streams enabled (not just metadata streams as is the default) is the only other file system that I would say does this well that isn't a work in progress (BTRFS).
IMO bitrot shouldn't be handled at the file system level to begin with, it should be done below the file...
There are also some legitimate reasons not to trust ZFS. The fragmentation issue ZFS suffers coupled with the variable sized blocks that require reference to block pointer trees that are often fragmented themselves will cause hdd heads to thrash during resilver if the pool has been used for any...
I read Micron's interpretation of the JEDEC spec on PMICs and it doesn't seem like there is a way to voltage lock them, the motherboard can manipulate the PMIC CAMP pin via the SPD hub connection via sideband I3C to set operational values. Perhaps the SPD hub IC could be co-opted to block...
True. I had wrongly assumed that the presence of the RCD on DIMM prevented any overclocking and that somehow the XMP implementation on RDIMM "unlocked" the RCD.
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