I've been looking over the DC optane population guide, but it wasn't clear about the case where you don't have DRAM in all memory channels. It seems to suggest, based on the iMC rules, for App Direct mode at least, that for a single CPU socket, supporting 6 or more memory slots supporting 6 memory channels, you should be able get away with oddball configurations.
For example, a common situation is a single CPU socket with 6 memory channels, in a 2+1+1 memory slot configuration for each iMC (8 memory slots total). If I read the guides correctly, it suggests you can get away with a 2x(Optane+DRAM,Optane,Optane) style configuration, for a max 6 DC optane per CPU socket for a 8 memory slot socket.
Most of the vendor DC optane config guides show minimum at least 1 DRAM module per memory channel (thus all channels active with DRAM), then 1 or more DC optane modules in the secondary memory slots per channel. They don't illustrate a low DRAM count configuration. Has anyone experienced using multiple DC optane when not all memory channels are filled with DRAM? Does that even work?
For example, a common situation is a single CPU socket with 6 memory channels, in a 2+1+1 memory slot configuration for each iMC (8 memory slots total). If I read the guides correctly, it suggests you can get away with a 2x(Optane+DRAM,Optane,Optane) style configuration, for a max 6 DC optane per CPU socket for a 8 memory slot socket.
Most of the vendor DC optane config guides show minimum at least 1 DRAM module per memory channel (thus all channels active with DRAM), then 1 or more DC optane modules in the secondary memory slots per channel. They don't illustrate a low DRAM count configuration. Has anyone experienced using multiple DC optane when not all memory channels are filled with DRAM? Does that even work?