AMD CES 2019 Keynote Announcements

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zir_blazer

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I spitted my coffee. AMD is going to use the MCM approach for AM4 Ryzens??? Seems inferior to a single monolithic die in such a simple design. Is AMD going to share the chiplets between EPYC Rome and consumer Ryzen and use different I/O dies, or are they the same I/O dies but heavily gutted?
 

Patrick

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I spitted my coffee. AMD is going to use the MCM approach for AM4 Ryzens??? Seems inferior to a single monolithic die in such a simple design. Is AMD going to share the chiplets between EPYC Rome and consumer Ryzen and use different I/O dies, or are they the same I/O dies but heavily gutted?
Based on what they showed, the Ryzen I/O die is much smaller.

The bigger savings is that they can use a leading-edge process for the cores and then an older process for the I/O.
 

AdrianB

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Based on what they showed, the Ryzen I/O die is much smaller.

The bigger savings is that they can use a leading-edge process for the cores and then an older process for the I/O.
Also, they have enough free space for a second 7-nm die, either for a second 8-core CPU or for an integrated GPU.

At least the variant with up to 16-cores is more or less confirmed now. Quote from the interview of Lisa Su published in PCWorld:


“Some people may have noticed on the package some extra room,” she said with a chuckle. “There is some extra room on that package and I think you might expect we will have more than eight cores.”
 
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wvaske

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Apr 12, 2017
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I spitted my coffee. AMD is going to use the MCM approach for AM4 Ryzens??? Seems inferior to a single monolithic die in such a simple design. Is AMD going to share the chiplets between EPYC Rome and consumer Ryzen and use different I/O dies, or are they the same I/O dies but heavily gutted?
I'd imagine the chiplets will be the same as that's one of the biggest benefits to NOT using a monolithic die for Ryzen. By sharing the same chiplet, the sellable yields will be higher. Chips not suitable for Epyc can be brought down the stack and pushed via Ryzen sales.

It's also effectively confirmed that they'll have SKUs with 2x 8-core chiplets. So it's a reduction in number of die they need to make as well.
 

Patrick

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@zir_blazer It somewhat depends right? There is only so much room on the package, but if AMD has PCIe Gen4 or a Gen4-based Infinity Fabric then that is going to be pretty good.
 

zir_blazer

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I'd imagine the chiplets will be the same as that's one of the biggest benefits to NOT using a monolithic die for Ryzen. By sharing the same chiplet, the sellable yields will be higher. Chips not suitable for Epyc can be brought down the stack and pushed via Ryzen sales.
That is in exchange of a latency increase because now the CPU chiplet has to go through the I/O die, whereas previously they were a single die. It also makes the package more complex and expensive, but I don't know by how much and how economy of scale would make that look against whatever they're gaining on die efficiency. For big things like Rome it makes sense, for AM4 Ryzens and APUs... I'l prefer to wait benchmarks.
I'm still skeptical about this approach, there should be some edge cases with regressions due to the increased latency. Alas, for people that now know that an 16C AM4 Ryzen is possible, they are going to be very happy either way.


Also, do we know already if the CPU CCX concept still exist or at least we can count on that the intradie chiplet latency is uniform?
 

browned

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Speculation so far for the CES Ryzen demo Eng Sample CPU 8 core/16 thread vs i9 9900K

- 3.7ghz base clock, 4.x all core boost.
- 65-75 Watts of power for CPU only.
- 20 Watts higher idle due to Eng Sample not having power management sorted yet.

Some are suggesting that the 8 core chips are now going to be the mid range R5, with 12 core being R7 and 16 core being R9. "If this is true" Intel's highest performance consumer CPU was just beaten by a low power mid range Ryzen R5.